Mechanism and method for reducing pipeline stalls between nested calls and digital signal processor incorporating the same
AssigneeLSI Logic Corporation
InventorHung T. Nguyen
Life of this patent
Estimating the term…
Abstract
For use in a wide-issue pipelined processor, a mechanism and method for reducing pipeline stalls between nested calls and supporting early prefetching of instructions in nested subroutines and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a program counter (PC) generator that generates return PC values for call instructions in a pipeline of the processor and (2) return PC storage, coupled to the PC generator and located in an execution core of said processor, that stores the return PC values and makes ones of the return PC values available to a PC of the processor upon execution of corresponding return instructions.
Claims22
For use in a wide-issue pipelined processor, a mechanism for reducing pipeline stalls between nested calls, comprising:
- a program counter (PC) generator configured to generate return PC values for multiple call instructions in a pipeline of said processor;
- and
- return PC storage, located in an execution core of said processor, coupled to said PC generator and including a PC queue and staging registers, said return PC storage configured to store said return PC values in said PC queue and, upon execution of a corresponding return instruction, make one of said return PC values available to a PC of said processor by employing said staging registers to track said corresponding return instruction while moving through stages in said pipeline.
For use in a wide-issue pipelined processor, a method of reducing pipeline stalls between nested calls, comprising:
- generating return PC values for call instructions in a pipeline of said processor;
- storing said return PC values in a PC queue of a return PC storage having staging registers and located in an execution core of said processor;
- and
- making one of said return PC values available to a PC of said processor upon execution of a corresponding return instruction by employing said staging registers to track said corresponding return instruction while moving through stages in said pipeline.
A digital signal processor, comprising:
- a pipeline having stages capable of executing call instructions;
- a wide-issue instruction issue unit;
- a program counter (PC) generator configured to return PC values for multiple call instructions in a pipeline of said processor;
- and
- return PC storage, located in an execution core of said processor, coupled to said PC generator and including a PC queue and staging registers, said return PC storage configured to store said return PC values in said PC queue and, upon execution of a corresponding return instruction, make one of said return PC values available to a PC of said processor by employing said staging registers to track said corresponding return instruction while moving through stages in said pipeline.
Dependencies are inferred from the claim text.