Integrated memory and method for setting the latency in the integrated memory
AssigneeInfineon Technologies AG
InventorAndreas Jakobs
Life of this patent
Estimating the term…
Abstract
An integrated memory has address inputs for applying a row address or a column address and a latency value, and an instruction decoder with a signal input. The instruction decoder uses a signal applied to the signal input to determine whether the address applied to the address inputs is the row address or the column address. If a column address is applied, an evaluation unit which is connected downstream of the instruction decoder and has evaluation inputs which are connected to the address inputs, is used to apply a latency signal corresponding to the latency value to an output of the evaluation unit.
Claims10
An integrated memory, comprising:
- address inputs for receiving a latency value and one of a row address and a column address;
- an instruction decoder having a signal input and a signal applied to said signal input being used to determine whether an address applied to said address inputs being the row address or the column address;
- and
- an evaluation unit connected downstream of said instruction decoder and having evaluation inputs connected to said address inputs and an output, said evaluation unit producing a latency signal corresponding to the latency value after receiving the column address and the latency value, the latency signal being available at said output.
A method for setting a latency in an integrated memory, which comprises the steps of:
- applying a column address and a latency value to address inputs of the integrated memory;
- carrying out a check to determine if the integrated memory has a memory access instruction applied to it;
- and
- using an evaluation unit to produce a latency signal on a basis of the latency value if the memory access instruction has been applied.
Dependencies are inferred from the claim text.