Memory control circuit outputting contents of a control register

A memory control circuit connected between a central processing unit (CPU) and a memory each of which outputs and receives data of a first bits, the memory control circuit comprising:

• a core circuit for conducting a refresh control, a precharge control and an access control of the memory, the core circuit having a first input terminal and a first output terminal;
• a first selection circuit having a first input terminal connected to the CPU, a second input terminal, and an output terminal connected to the first input terminal of the core circuit, the first selection circuit selecting input in response to a mode signal;
• a first test data input terminal receiving a first test data of a second bits that is smaller than the first bits;
• a first extension circuit connected between the first test data input terminal and the second input terminal of the first selection circuit, the first extension circuit extending the first test data of the second bits to a first extended test data of the first bits;
• a first degeneration circuit connected to the first output terminal of the core circuit, the first degeneration circuit compressing data of the first bits received from the core circuit to a first output data of the second bits;
• and
• a second selection circuit having a first input terminal connected to the first output terminal of the core circuit, a second input terminal connected to the first degeneration circuit and an output terminal, the second selection circuit selecting input in response to a test signal.

A memory control circuit connected to a central processing unit (CPU), a first memory and a second memory each of which outputs and receives data of a first bits, the memory control circuit comprising:

• a first core circuit for conducting a refresh control, a precharge control and an access control of the first memory, the first core circuit having a first input terminal and a first output terminal;
• a second core circuit for conducting a refresh control, a precharge control and an access control of the second memory, the second core circuit having a first input terminal and a first output terminal;
• a first selection circuit having a first output terminal connected to the first input terminal of the first core circuit, a second output terminal connected to the first input terminal of the second core circuit and an input terminal, the first selection circuit selecting output in response to a memory selection signal;
• a second selection circuit having a first input terminal connected to the CPU, a second input terminal, and an output terminal connected to the input terminal of the first selection circuit, the second selection circuit selecting input in response to a mode signal;
• a first test data input terminal receiving a first test data of a second bits that is smaller than the first bits;
• a first extension circuit connected between the first test data input terminal and the second input terminal of the second selection circuit, the first extension circuit extending the first test data of the second bits to a first extended test data of the first bits;
• a third selection circuit having a first input terminal connected to the first output terminal of the first core circuit, a second input terminal connected to the first output terminal of the second core circuit and an output terminal, the third selection circuit selecting in one of an output of the core circuit and an output of the second core circuit in response to the memory selection signal;
• a first degeneration circuit connected to the output terminal of the third selection circuit, the first degeneration circuit compressing data of the first bits received from the output terminal of the third selection circuit to a first output data of the second bits;
• and
• a fourth selection circuit having a first input terminal connected to the output terminal of the third selection circuit, a second input terminal connected to the first degeneration circuit and an output terminal, the fourth selection circuit selecting input in response to a test signal.