Arbitration apparatus utilizing mutlilevel priority for reducing memory access time
AssigneeNEC Corporation
InventorTetsuro Takizawa
Life of this patent
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Abstract
Probabilities of the changeovers of access pages in the same bank and the changes of types of accesses, for instance the change from read to write or from write to read, are reduced and thereby data transmission performance is improved. If respective memory masters want to acquire the memory use right, they assert request signals and, at the same time, fix address signals and read/write signals. A memory arbitration circuit determines the priority order over the memory use right for the respective memory masters, and asserts an acknowledgement signal for a memory master having the highest priority.
Claims36
An arbitration apparatus comprising:
- a plurality of memory masters each outputting a request signal for requesting a memory use right;
- and
- a memory arbitration circuit for giving the memory use right to one of the memory masters selected from the memory masters which have output the request signals,
- wherein the memory masters each output signals that indicate access attributes to the memory when outputting the request signal,
- wherein when plural memory masters have output the request signals, the memory arbitration circuit gives the memory use right to a memory master selected from the memory masters based on the signals indicating the access attributes.
- wherein the memory arbitration circuit assigns low priority to a first memory master outputting the address signal indicating a first memory bank that is the same as the one that has been accessed up to that time, assigns high priority to a second memory master outputting the address signal indicating a memory bank different from the one that has been accessed up to that time and, when only one memory master is given high priority, gives the memory use right to the one memory master.
An arbitration apparatus comprising:
- a plurality of memory masters each outputting a request signal for requesting a memory use right;
- and
- a memory arbitration circuit for giving the memory use right to one of the memory masters selected from the memory masters which have output the request signals,
- wherein the memory masters each output signals that indicate access attributes to the memory when outputting the request signal;
- wherein when plural memory masters have output the request signals, the memory arbitration circuit gives the memory use right to a memory master selected from the memory masters based on the signals indicating the access attributes;
- wherein the signals that indicate the access attributes include:
- an address signal for indicating the address of the memory to access;
- and a read/write signal for indicating whether the access to the address is a read access or a write access;
- and
- wherein the memory arbitration circuit is provided with a prescribed threshold setting in advance to compare elapsed time after a last request signal output of each memory master with the threshold, and assigns high priority to a first memory master in which elapsed time is above the threshold, assigns low priority to a second memory master outputting the address signal indicating a memory bank same as the memory bank that has been accessed up to that time, assigns medium priority to a third memory master outputting the address signal indicating a memory bank different from the one that has been accessed up to that time and, when only one memory master is given high priority, gives the memory use right to the one memory master.
The arbitration apparatus claimed in 12, wherein, the memory arbitration circuit is provided with the fixed priority order setting in advance and, when there are plural memory masters assigned with medium priority while no memory master has been given high priority, gives the memory use right to a memory master having a highest priority among the memory masters according to the fixed priority order setting.
Dependencies are inferred from the claim text.