Systems and methods for addressing memory

A computerized system, comprising:

• a set of processors;
• memory;
• and
• an addressing circuit coupled to the set of processors and the memory, the addressing circuit being configured to address the memory, the addressing circuit including:
• a first set of inputs coupled to the set of processors, the first set of inputs being configured to receive a first set of address signals en route from the set of processors to the memory, the first set of address signals defining a least significant address portion;
• a second set of inputs coupled to the set of processors, the second set of inputs being configured to intercept a second set of address signals en route from the set of processors to the memory, the second set of address signals defining a most significant address portion;
• and
• control circuitry coupled to the first and second sets of inputs, the control circuitry being configured to output a replacement set of address signals to the memory in place of the second set of address signals, the replacement set of address signals defining one of (i) the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, and (ii) a predefined most significant address portion when the least significant address portion is within the predetermined range.

An addressing circuit for addressing memory, the addressing circuit comprising:

• a first set of inputs configured to receive a first set of address signals en route from a set of processors to the memory, the first set of address signals defining a least significant address portion;
• a second set of inputs configured to intercept a second set of address signals en route from the set of processors to the memory, the second set of address signals defining a most significant address portion;
• and
• control circuitry coupled to the first and second sets of inputs, the control circuitry being configured to output a replacement set of address signals to the memory in place of the second set of address signals, the replacement set of address signals defining one of (i) the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, and (ii) a predefined most significant address portion when the least significant address portion is within the predetermined range.

An addressing circuit for addressing memory, the addressing circuit comprising:

• a first set of inputs configured to receive a first set of address signals en route to the memory, the first set of address signals defining a least significant address portion;
• a second set of inputs configured to intercept a second set of address signals en route to the memory, the second set of address signals defining a most significant address portion;
• and
• means for outputting a replacement set of address signals to the memory in place of the second set of address signals, the replacement set of address signals defining one of (i) the most significant address portion defined by the second set of address signals when the least significant address portion is outside a predetermined range, and (ii) a predefined most significant address portion when the least significant address portion is within the predetermined range.