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US 7,013,360 B2Granted
Efficient use of multiple buses for a scalable and reliable high-bandwidth connection
AssigneeIntel Corporation
InventorDavid M. Lee
Life of this patent
Estimating the term…
Abstract
In one embodiment, a system is disclosed having a first device, a second device, and two sets of bi-directional buses that couple the first and second devices. The devices are to perform transactions with each other over the buses, such that each set of buses has a dominant, but not exclusive, direction, for sending transaction information and data, that is opposite the other. Other embodiments are also described and claimed.
Claims13
An integrated circuit (IC) device, comprising:
- a first bus interface unit to send a transaction packet over a first bus and not a second bus;
- a second bus interface unit to send a transaction packet over the second bus and not the first bus;
- and
- a queue to store information that characterizes a plurality of bus transactions to be claimed by one of the first and second bus interface units and performed over one of the first and second buses,
- wherein the IC device can be configured to operate in a first way that does not give either bus interface unit preference over the other when claiming a transaction from the queue,
- and wherein the IC device can be configured to operate in a second way in which the first bus interface unit is preferred over the second bus interface unit when claiming a transaction from the queue.
3 more elements
An integrated circuit (IC) device, comprising:
- a first bus interface unit to send transaction information over a first bus and not a second bus, the first bus interface unit having a bus arbiter and a send block;
- a second bus interface unit to send transaction information over the second bus and not the first bus;
- and
- a queue to store information that characterizes a plurality of bus transactions to be claimed by one of the first and second bus interface units for being performed over one of the first and second buses,
- wherein the send block is to a) monitor the queue for transactions that are ready to be performed, b) request the first bus through the arbiter, and c) format and send a transaction packet into the first bus,
- wherein the arbiter gives preference to the send block over other bus agents in response to a preference signal being asserted.
3 more elements
An integrated circuit (IC) device, comprising:
- a first bus interface unit to send a transaction packet over a first bus and not a second bus;
- a second bus interface unit to send a transaction packet over the second bus and not the first bus;
- and
- a queue to store information that characterizes a plurality of bus transactions to be claimed by one of the first and second bus interface units for being performed over one of the first and second buses,
- wherein to prevent the same transaction from being sent over two buses simultaneously, one of the first and second bus interface units, which is preferred over the other, is to block the other when claiming a transaction from the queue.
2 more elements
A method for performing bus transactions using multiple buses, comprising:
- sending a transaction packet over a first bus and not a second bus, using a first bus interface;
- sending a transaction packet over the second bus and not the first bus, using a second bus interface;
- buffering information that characterizes a plurality of bus transactions to be claimed by one of the first and second bus interfaces to be performed over one of the first and second buses;
- operating the bus interfaces in a first way that does not give either bus interface preference over the other when claiming a buffered transaction;
- and
- operating the bus interfaces in a second way in which the first bus interface is preferred over the second bus interface when claiming a buffered transaction.
3 more elements
Dependencies are inferred from the claim text.