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US 7,013,348 B1Granted
Switch subtending in a synchronous transmission system
AssigneeNortel Networks Limited
InventorsMark Carson, David M. Goodman
Life of this patent
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AssigneeNortel Networks Limited
InventorsMark Carson, David M. Goodman
Estimating the term…
The invention concerns a switching apparatus comprising a low order switch subtended from a high order switch. In order to compensate for delays incurred by passing a data frame through the high order switch to the low order switch and delays incurred by the operation of the low order switch, the apparatus is arranged to advance the payload of a received data frame with respect to the fixed overhead of the data frame by an amount corresponding to the incurred delays. The low order switch uses the advanced payload to create an output frame, for sending to the high order switch, which is advanced with respect to the data frame that it receives. The apparatus, which is particularly suitable for use in SDH and/or SONET systems, obviates the need to provide an alignment apparatus, such as a VT/TU aligner between the high order switch and the subtended low order switch.
An apparatus for switching data frames comprising payload data arranged in accordance with a normal frame structure that includes high order data structures and low order data structures, the apparatus comprising a first switching component for switching high order data structures;
In an apparatus for switching data frames comprising payload data arranged in accordance with a normal data frame structure that includes high order data structures and low order data structures, the apparatus comprising a first switching component for switching high order data structures;
An apparatus for switching low order data structures, the apparatus being arranged to receive an input data frame comprising payload data and to generate an output data frame comprising payload data, wherein the apparatus further includes a plurality of data memories and is arranged to, in respect of a received data frame, write successive blocks of received payload data in sequence to said memories and, in order to create an output data frame, to read blocks of payload data in sequence from said memories, the respective sequences being such that while data is being written to one memory, data is being read from another memory, wherein the writing and reading of data to and from the memories is controlled by respective independent timing reference signals.
Dependencies are inferred from the claim text.