Digital filter methods and structures for increased processing rates

A digital filter, comprising:

• a divider that responds to an input clock signal that has an input rate and provides a reduced clock signal that has a reduced rate;
• at least one buffer register that receives an input data stream of data elements and provides a delayed data stream;
• at least two latches arranged to receive respective ones of said input and delayed data streams and provide data substreams in response to said reduced clock signal;
• for each respective one of said data substreams, a set of buffer registers that receive and successively delay data elements of said respective data substream;
• multipliers arranged to multiply received data elements and data elements from said buffer registers with stored filter coefficients to thereby provide products;
• and
• for each respective one of said data substreams a set of summers arranged to sum said products and thereby generate an output data signal.

A digital filter, comprising:

• a divider that responds to an input clock signal that has an input rate and provides a reduced clock signal that has a reduced rate;
• a buffer store that receives an input data stream of data elements and provides at least one delayed data stream;
• at least two latches arranged to receive respective ones of said input and delayed data streams and provide latched data substreams in response to said reduced clock signal;
• and
• at least one data processor programmed to convolve each of said data substreams with stored filter coefficients to thereby generate a respective one of output data signals.