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US 7,013,256 B2Granted
Computer system with debug facility
AssigneeSTMicroelectronics S.r.l.
InventorsAndrew Cofler, Laurent Wojcieszak, Arnaud Dehamel, Isabelle Sename
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AssigneeSTMicroelectronics S.r.l.
InventorsAndrew Cofler, Laurent Wojcieszak, Arnaud Dehamel, Isabelle Sename
Estimating the term…
A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.
A computer system for executing instructions having assigned guard indicators, which system comprises instruction supply circuitry, at least one pipelined execution unit for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, said execution unit including a master guard value store containing master values for the guard indicators in said set of guard indicators, and circuitry for resolving the guard value of the or each guard indicator in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, said system including an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronizing circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.
A method of executing instructions in a computer system, said instructions having assigned guard indicators, and effecting a debugging watch on execution of said instructions, which method comprises supplying a plurality of instructions to at least one pipelined execution unit, resolving the guard value of each instruction in the execution unit to provide a commit signal if the instruction is executed, and effecting a debugging watch by selecting instructions in an instruction fetch operation and providing a program count signal for said selected instructions, storing the program count in a sequential buffer, and storing in a further sequenced buffer commit signals derived from resolution of the guard value in the execution pipeline thereby synchronizing the program count with resolution of the guard value for the selected instruction.
Dependencies are inferred from the claim text.