Low-complexity, high accuracy model of a CPU power distribution system
AssigneeSun Microsystems, Inc.
InventorsClaude R. Gauthier, Brian W. Amick
Life of this patent
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Abstract
A low-complexity, high accuracy model of a CPU power distribution system has been developed. The model includes models of multiple power converters that input to a board model. The board model then inputs to a package model. Finally, the package model inputs to a chip model. The model provides a high degree of accuracy with an acceptable simulation time.
Claims31
An apparatus for modeling a power system of a microprocessor based system, comprising:
- a plurality of power converter models;
- a board model that receives an output from the plurality of power converter models;
- a package model that receives an output from the board model;
- and
- a chip model that receives an output from the package model, wherein the chip model further comprises:
- a plurality of bump and grid models;
- a plurality of section models that receives a plurality of outputs from the plurality of bump and grid models, wherein each of the plurality of section models further comprises a load model;
- and
- a plurality of channel models that interconnect the plurality of section models.
An apparatus for modeling a power system of a microprocessor based system, comprising:
- means for modeling a power converter;
- means for modeling a board that receives an output from the means for modeling a power converter;
- means for modeling a package that receives an output from the means for modeling a board;
- and
- means for modeling a chip that receives an output from the means for modeling a package, wherein the means for modeling a chip further comprises:
- means for modeling a plurality of bumps and grids;
- means for modeling a plurality of sections that receive a plurality of outputs from the plurality of bumps and grids, wherein each of the plurality of sections further comprises a load model;
- and
- means for modeling a plurality of channel models that interconnect the plurality of sections.
A method for modeling a power system of a microprocessor based system, comprising:
- modeling a plurality of power converters;
- modeling a board that receives an output from the plurality of power converter;
- modeling a package that receives an output from the board;
- and
- modeling a chip that receives an output from the package, wherein modeling a chip further comprises:
- modeling a plurality of bump and grid components;
- modeling a plurality of chip sections that receives an output from the plurality of bump and arid components, wherein modeling a plurality of chip sections further comprises modeling a load;
- and
- modeling a plurality chip channels that interconnects the plurality of chip sections.
An apparatus for modeling a power system of a microprocessor chip, comprising:
- a plurality of bump and grid models;
- a plurality of section models that receives a plurality of outputs from the plurality of bump and grid models, wherein the plurality of section models further comprises a load model;
- and
- a plurality of channel models that interconnect the plurality of section models.
An apparatus for modeling a power system of a microprocessor chip, comprising:
- means for modeling a plurality of bumps and grids;
- means for modeling a plurality of sections that receives a plurality of outputs from the plurality of bumps and grids, wherein means for modeling a plurality of sections further comprises means for modeling a load;
- and
- means for modeling a plurality of channels that interconnect the plurality of sections.
A method for modeling a power system of a microprocessor chip, comprising:
- modeling a plurality of bump and grid components;
- modeling a plurality of chip sections that receives an output from the plurality of bump and grid components, wherein modeling a plurality of chip sections further comprises modeling a load;
- and
- modeling a plurality chip channels that interconnect the plurality of chip sections.
Dependencies are inferred from the claim text.