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US 7,012,297 B2Granted
Scalable flash/NV structures and devices with extended endurance
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.
Claims46
A gate stack, comprising:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
1 more element
A gate stack, comprising:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes nano crystals for providing charge trapping charge centers;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
1 more element
A memory cell, comprising:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
6 more elements
A nonvolatile memory device, comprising:
- an array of memory cells operably coupled to a grid of row lines and column lines;
- row select circuitry for selecting a row of memory cells;
- and
- column select circuitry for selecting a column of memory cells,
- wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage;
- and
- wherein each memory cell includes:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
13 more elements
An electronic system, comprising:
- a processor;
- and
- a nonvolatile memory device coupled to the processor, the nonvolatile memory device including:
- an array of memory cells operably coupled to a grid of row lines and column lines;
- row select circuitry for selecting a row of memory cells;
- and
- column select circuitry for selecting a column of memory cells,
- wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage;
- and
- wherein each memory cell includes:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
16 more elements
A gate stack, comprising:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes silicon-rich Al2O3;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
1 more element
A memory cell, comprising:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes silicon-rich Al2O3;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
6 more elements
A nonvolatile memory device, comprising:
- an array of memory cells operably coupled to a grid of row lines and column lines;
- row select circuitry for selecting a row of memory cells;
- and
- column select circuitry for selecting a column of memory cells,
- wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage;
- and
- wherein each memory cell includes:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes silicon-rich Al2O3;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
13 more elements
An electronic system, comprising:
- a processor;
- and
- a nonvolatile memory device coupled to the processor, the nonvolatile memory device including:
- an array of memory cells operably coupled to a grid of row lines and column lines;
- row select circuitry for selecting a row of memory cells;
- and
- column select circuitry for selecting a column of memory cells,
- wherein the row select circuitry and the column select circuitry cooperate to select a memory cell in the selected row and the selected column for application of a programming voltage;
- and
- wherein each memory cell includes:
- a substrate including diffused regions that form a source region and a drain region;
- a gate stack disposed on the substrate between the source region and the drain region;
- and
- a gate disposed on the gate stack,
- wherein the gate stack includes:
- a tunnel medium;
- a high K charge blocking and charge storing medium disposed on the tunnel medium, wherein the high K charge blocking and charge storing medium includes silicon-rich Al2O3;
- and
- an injector medium operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling.
16 more elements
Dependencies are inferred from the claim text.