Bottom-up approach for synthesis of register transfer level (RTL) based design

A method of synthesizing a register transfer level (RTL) based design of a system comprising the steps of:

• determining a plurality of sub-modules of a top level system;
• determining individual time budgets for each sub-module based on timing requirements of the top-level system;
• synthesizing a gate level design of—said each sub-module based on the determined time budgets for said each sub-module;
• testing the gate level design of said each sub-module for conformance with design requirements of said each sub-module;
• generating a netlist for said each sub-module when the gate level design of said each sub-module conforms to said design requirements of said each sub-module, then integrating the netlist of said each sub-module to form an integrated top level design netlist;
• testing the integrated top-level design netlist for conformance with top-level design requirements;
• and
• generating a top-level netlist when the integrated top-level design netlist conforms to the top-level design requirements,
• wherein testing the gate level design of said each sub-module includes performing static timing analysis on said each sub-module for conformance with timing requirements for said each sub-module.

A method of synthesizing a register transfer level (RTL) based design of a system comprising the steps of:

• determining sub-modules of a top level system;
• determining individual time budgets for each sub-module based on timing requirements of the top-level system;
• synthesizing a gate level design of said each sub-module based on the determined time budgets for said each sub-module;
• generating a netlist for the gate level design of said each sub-module;
• integrating the netlist of said each sub-module to form an integrated top level design netlist;
• testing the integrated top-level design netlist for conformance with top-level design requirements;
• generating a top-level netlist when the integrated top-level design netlist conforms to the top-level design requirements;
• and
• testing the gate level design of said each sub-module for conformance with design requirements of said each sub-module prior to integrating the netlists to form the integrated top-level design netlist, wherein
• testing the gate level design of said each sub-module includes performing static timing analysis on said each sub-module for conformance with timing requirements for said each sub-module, and
• the netlist for the gate level design of said each sub-module is generated only if the timing requirements for said each sub-module are met.