Method and circuit for error correction in CAM cells

A method for detecting and correcting errors in an array of content addressable memory (CAM) cells coupled to wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching data in the CAM cells, said method comprising the steps of:

• (a) storing a row parity bit in a row parity CAM cell coupled to the matchline of an associated row, said row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells;
• (b) storing a column parity bit in a column parity CAM cell coupled to the bitline of an associated column, said column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells;
• (c) reading and generating a parity of said first plurality of bits and comparing said generated parity to said stored row parity bit;
• (d) if said generated and stored parity bits do not match;
• (i) cycling through columns of said array;
• (ii) reading and generating a parity of said second plurality of bits and comparing said generated parity to said stored column parity bit until a mismatch is indicated;
• and
• (iii) inverting a bit located at an intersection of said mismatched row and said column if said mismatch is indicated.

A circuit for writing data to a content addressable memory (CAM) cell in an array of CAM cells, said array including a parity row and a parity column for error correction and wordlines, bitlines, searchlines, and matchlines for reading from, writing to, and searching CAM cells in said array, said circuit comprising:

• (a) a read sense amplifier for receiving previously stored data from said bitlines;
• (b) a read latch for latching said previously stored data;
• (c) a read driver for driver for driving said previously stored data onto a databus;
• (d) a write latch for latching new data to be written;
• (e) a write driver for driving said new data to said bitlines;
• wherein the parity row comprising at least one column parity CAM cell coupled to the bitline of an associated column, the parity column comprising at least one row parity CAM cell coupled to the matchline of an associated row;
• and
• wherein if said data read from said previously stored data is different from said new data, a corresponding column parity bit in said parity row is changed.