US 7,010,736 B1 · Address sequencer within BIST (Built-in-Self-Test) system

Abstract

An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

Claims28

Dependent claims

A method for sequencing through flash memory cells fabricated on a semiconductor substrate, including the steps of:

fabricating a plurality of logic units of an address sequencer control logic and address sequencer buffers on the semiconductor substrate;
generating a plurality of bits by the buffers for indicating an address of the flash memory cells;
and
controlling, by a respective different logic unit of the control logic, the buffers to sequence through a respective different sequence of bit patterns for each of a plurality of different types of BIST (built-in-self-test) modes,
wherein a different unique logic unit controls the buffers to sequence through a different unique sequence of bit patterns for each of the different types of BIST modes.

2 more elements

A system for sequencing through flash memory cells fabricated on a semiconductor substrate, comprising:

address sequencer buffers, fabricated on the semiconductor substrate, for generating a plurality of bits that indicate an address of the flash memory cells;
and
a plurality of logic units of an address sequencer control logic, fabricated on the semiconductor substrate, a respective different logic unit controlling the buffers to sequence through a respective different sequence of bit patterns for each of a plurality of different types of BIST (built-in-self-test) modes,
wherein a different unique logic unit controls the buffers to sequence through a different unique sequence of bit patterns for each of the different types of BIST modes.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

10/200,518Filed 22 Jul 2002

Granted

7 Mar 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

G11C 29/36
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: data generation devices, e.g. data inverters
G11C 29/12005
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: comprising voltage or current generators
G11C 29/16
Implementation of control logic, e.g. test mode decoders: using microprogrammed units, e.g. state machines
G11C 29/18
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: address generation devices; Devices for accessing…

Address sequencer within BIST (Built-in-Self-Test) system

Life of this patent

Address sequencer within BIST (Built-in-Self-Test) system

Life of this patent

Abstract

Claims28