Stuck-at fault scan chain diagnostic method

A method for testing combinational and sequential logic circuits where memory units are coupled together to form shift register latches, arranged in a shift register scan path with an input and output for testing the logic circuits, the method comprising:

• determining a stuck-at fault condition exists in one of the shift register latches;
• shifting data through the scan path to load the shift register latches with a first data pattern representative of the outputs state as a result of the stuck-at fault condition and thus introducing said data into an inaccessible latch in a stuck-at fault LSSD chain;
• causing permutation of at least one of the following operating parameters:
• a supply voltage;
• a reference voltage;
• a timing pattern temperature and a timing sequence to trigger a change in state from the stuck-at fault state of at least one of the memory units in the shift register scan path for the purpose of locating stuck-at fault bits in said stuck-at fault LSSD chain;
• and
• determining the memory unit furthest from the shift register scan path output that has changed state from its loaded value for the purpose of locating stuck-at fault bits in said at least one of the memory units.

A computer program on a media usable with a computer for testing combinational and sequential logic circuits where memory units are coupled together to form shift register latches that are arranged in a shift register scan path with an input and output for testing the logic circuits, said computer program comprising:

• stuck fault detection code for detecting a stuck-at fault output level of the shift register scan path from an expect state;
• a load pattern computer code for shifting data through the scan path to load the shift register latches of the scan path with the detected stuck-at fault output level condition and thus introducing said data into an inaccessible latch in a stuck-at fault LSSD chain;
• pattern variation computer code for causing permutation of at least one of the following operating parameters:
• a supply voltage, a reference voltage, a timing pattern temperature and a timing sequence to trigger a change in state of at least one of the memory units in the shift register scan path that is detectable at the output of the shift register scan path for the purpose of locating stuck-at fault bits in said stuck-at fault LSSD chain;
• and
• analyzing computer code for determining the memory unit furthest from the shift register scan path output that has changed state from its loaded value as a result of permutations of an operating parameter for the purpose of locating stuck-at fault bits in said at least one of the memory units.