Method for microprocessor test insertion reduction
AssigneeSun Microsystems, Inc.
InventorsUpendra S. Brahme, Donald E. Fox
Life of this patent
Estimating the term…
Abstract
Methods for reducing the requirement for multiple test vector sub-set insertions of a test vector set on test equipment having a limited memory size. In one embodiment, a single, selective test vector sub-set is utilized in the pre-burn-in test phase of microprocessors and multiple test vector sub-set insertions of a test vector set are utilized in the post-burn-in test phase. In one embodiment, the single, selective test vector sub-set includes selected test vectors from some or all of the test vector sub-sets used in the post-burn-in test phase and is sized to fit within the fixed memory capacity of the test equipment. In another embodiment, a single, selective test vector sub-set is utilized in both the pre-burn and post-burn test phases.
Claims11
A method for testing one or more microprocessors for defects on test equipment having a fixed memory capacity, the method comprising:
- loading a single, selective test vector sub-set into a fixed memory of test equipment, the selective test vector sub-set further comprising one or more selected test vectors, the selective test vector sub-set being less than or equal to the memory capacity of the test equipment;
- executing the selective test vector sub-set on the test equipment prior to burning in the one or more microprocessors, execution of the selective test vector sub-set causing the test equipment to test the microprocessors with the one or more selected test vectors;
- executing a burn-in of the one or more microprocessors;
- after burning in the one or more microprocessors, loading a first test vector sub-set into the fixed memory of the test equipment, the first test vector sub-set being one segment of a test vector set, the first test vector sub-set further comprising a first sub-set of test vectors;
- executing the first test vector sub-set on the test equipment, execution of the first test vector sub-set causing the test equipment to test the one or more microprocessors with the first sub-set of test vectors;
- loading a second test vector sub-set into the fixed memory of the test equipment, the second test vector sub-set being another segment of the test vector set, the second test vector sub-set further comprising a second sub-set of test vectors;
- and
- executing the second test vector sub-set on the test equipment, execution of the second test vector sub-set causing the test equipment to test the one or more microprocessors with the second sub-set of test vectors.
A method for testing one or more microprocessors for defects on test equipment having a fixed memory capacity, the method comprising:
- loading a single, selective test vector sub-set into a fixed memory of test equipment, the selective test vector sub-set further comprising one or more selected test vectors, the selective test vector sub-set being less than or equal to the memory capacity of the test equipment;
- executing the selective test vector sub-set on the test equipment prior to burning in the one or more microprocessors, execution of the selective test vector sub-set causing the test equipment to test the microprocessors with the one or more selected test vectors;
- executing a burn-in of the one or more microprocessors;
- loading the single, selective test vector subset into the fixed memory of the test equipment;
- and
- executing the selective test vector sub-set on the test equipment after burning in the one or more microprocessors, execution of the selective test vector sub-set causing the test equipment to test the microprocessors with the one or more selected test vectors.
Dependencies are inferred from the claim text.