Prescaler architecture capable of non integer division
AssigneeLSI Logic Corporation
InventorDavid P. Tester
Life of this patent
Estimating the term…
Abstract
A prescaler generally comprising a first circuit, a multiplexer, and a second circuit. The first circuit may be configured to present a plurality of control signals in response to a first clock signal having a first frequency. The multiplexer may be configured to multiplex a plurality of data signals in response to the control signals to present a second clock signal having a second frequency that is a non-integer fraction of the first frequency. The second circuit may be configured to present the data signals in response to the second clock signal.
Claims22
A prescaler comprising:
- a first circuit configured to generate a plurality of control signals in response to a first clock signal having a first frequency;
- a multiplexer configured to multiplex a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;
- a second circuit configured to (i) generate said data signals in response to said second clock signal and (ii) present said data signals directly to said multiplexer;
- a first dividing circuit configured to divide said second clock signal by a first predetermined integer to present a third clock signal;
- and
- a second dividing circuit configured to divide said third clock signal by a second predetermined integer to present a fourth clock signal.
A method of dividing a first clock signal having a first frequency, the method comprising the steps of:
- (A) generating a plurality of control signals in response to said first clock signal;
- (B) multiplexing a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;
- (C) generating said data signals in response to said second clock signal;
- (D) presenting said data signals directly to said multiplexing;
- (E) dividing said second clock signal by a first predetermined integer to present a third clock signal:
- and
- (F) dividing said third clock signal by a second predetermined integer to present a fourth clock signal.
A prescaler comprising:
- means for generating a plurality of control signals in response to a first clock signal having a first frequency;
- means for multiplexing a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;
- means for generating said data signals in response to said second clock signal;
- means for dividing said second clock signal by a first predetermined integer to present a third clock signal;
- and
- means for dividing said third clock signal by a second predetermined integer to present a fourth clock signal.
A prescaler comprising:
- a first circuit configured to generate a plurality of control signals in response to a first clock signal having a first frequency;
- a multiplexer configured to multiplex a plurality of data signals in response to said control signals to present a second clock signal having a second frequency that is a non-integer fraction of said first frequency;
- a second circuit configured to generate said data signals in response to said second clock signal;
- a first dividing circuit configured to divide said second clock signal by a first predetermined integer to present a third clock signal;
- a second dividing circuit configured to divide said third clock signal by a second predetermined integer to present a fourth clock signal;
- a gating circuit configured to gate said second clock signal received by said second circuit in response to said third clock signal and said fourth clock signal;
- and
- a selection circuit configured to control said fourth clock signal to select a modulus of division of said first clock signal.
Dependencies are inferred from the claim text.