Physical layer device with output buffer for link pulse generator connected to cascaded power sub-circuts that receive a series of disabling signals
AssigneeVIA Technologies, Inc.
InventorsMing-Hsun Hsu, Chien-Cheng Chang, Yu-En Tzeng
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Abstract
A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of outputting a plurality of link pulses, asserting a plurality of disabling signals between two adjacent link pulses for disabling the sub-circuits, respectively, and deasserting the disabling signals for enabling the sub-circuits, respectively. The disabling signals are asserted separately for disabling the sub-circuits at different time points. A physical layer device for use in a chip for saving electrical power is also disclosed.
Claims10
A physical layer (PHY) device for use in a chip, comprising:
- a link pulse generator generating a series of link pulses;
- an output buffer electrically connected to said link pulse generator for receiving and then outputting either of data or said link pulses;
- a power source circuit electrically connected to said output buffer and comprising a plurality of sub-circuits cooperating to provide power for said output buffer;
- and
- a disabling signal generator electrically connected to said link pulse generator and said sub-circuits of said power source circuit for detecting said link pulses, and asserting a series of disabling signals to disable said sub-circuits after the generation of a preceding one of said link pulses, and deasserting said disabling signals to enable said sub-circuits before the generation of a following one of said link pulses.
Dependencies are inferred from the claim text.