Apparatus and method for processing pipelined data

A module (1) for processing pipelined data, comprising a classification means (2) for matching or identifying a block (4) of data and a processing means (3) for processing the block (4), the processing means (3) connected to storage means and comprising at least two logic units (11) for executing operations on the block (4), which is delivered from the classification means (2) to the processing means (3), wherein the processing means comprises a first register for storing a program counter, the classification means being connected to the first register for storing a program counter,

• the storage means comprises a first instruction table (12a) comprising at least one instruction,
• a first logic unit (11) is connected to a first register (10a) for storing the block,
• the first register for storing a first program counter is connected to the first instruction table,
• the first instruction table is connected to the first logic unit,
• the first logic unit is connected to a further register (10d) for storing the block of data, and to a further register (10f) for storing a second program counter,
• a second logic unit (14) is connected to the further register (10d) for storing the block of data,
• the further register (10f) for storing a second program counter is connected to a second instruction table (12b), wherein the second instruction table is connected to the second logic unit (14).

A circuit board assembly (16), such as a line card (23a) adapted for a router, having at least one integrated circuit (15) comprising at least one module (1) for processing pipelined data, wherein said module comprising a classification means (2) for matching or identifying a block (4) of data and a processing means (3) for processing the block (4), the processing means (3) being connected to storage means and comprising at least two logic units (11) for executing operations on the block (4), which is delivered from the classification means (2) to the processing means (3), and wherein

• the processing means comprises a first register (10c) for storing a program counter, the classification means being connected to the first register for storing a program counter,
• wherein the storage means comprises a first instruction table (12a) comprising at least one instruction,
• a first logic unit (11) is connected to a first register (10a) for storing the block, the first register for storing a first program counter is connected to the first instruction table (12a), the first instruction table (12a) is connected to the first logic unit (11), the first logic unit is connected to a further register (10d) for storing the block of data, and to a further register (10f) for storing a second program counter, and
• a second logic unit (14) is connected to the further register (10d) for storing the block of data, the further register (10f) for storing a second program counter is connected to a second instruction table (12b), wherein the second instruction table is connected to the second logic unit (14).

A pipelined processing system, comprising a classification means (2) for matching or identifying a block (4) of data, a storage means and a processing means (3) for processing the block (4), the processing means (3) being connected to storage means and comprising at least two logic units (11) for executing operations on the block (4), which is delivered from the classification means (2) to the processing means (3), wherein,

• the processing means comprises a first register for storing a program counter, the classification means being connected to the first register for storing a program counter,
• the storage means comprises a first instruction table (12a) comprising at least one instruction,
• a first logic unit (11) is connected to a first register for storing the block,
• the first register for storing a first program counter is connected to the first instruction table (12a),
• the first instruction table (12a) is connected to the first logic unit (11),
• the first logic unit is connected to a further register (10d) for storing the block of data,
• and to a further register (10f) for storing a second program counter,
• a second logic unit (14) is connected to the further register (10d) for storing the block of data,
• the further register (10f) for storing a second program counter is connected to a second instruction table (12b), and
• the second instruction table (12b) is connected to the second logic unit (14).