US 7,010,670 B2 · Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer

Abstract

The invention provides a data processing device with which disadvantages due to instruction allocation and decreased memory when adding a condition specifying field for executing conditional instructions can be prevented, and in which pipeline hazards due to the non-fulfillment of conditions can be suppressed when instructions with contradicting conditions are performed successively. The data processing device reads in and executes instructions in a certain sequence, and includes a fetch portion for reading in a computational instruction, a decoding portion for decoding the computational instruction that has been read in, an execution portion for executing the decoded computational instruction, and an instruction overriding control circuit that overrides, of one or a plurality of subsequent instructions that follow the computational instruction in said sequence and are associated with the computational instruction, all but one of the subsequent instructions, in accordance with an execution result of the computational instruction.

Claims18

Dependent claims

A data processing device programmed for reading in and executing instructions in a certain sequence, the data processing device comprising:

a fetch portion for reading in a computational instruction;
a decoding portion for decoding the computational instruction that has been read in;
an execution portion for executing the computational instruction in accordance with a decoding of the computational instruction;
a sequencer for updating an output to one of at least three different states as a conditional execution status in response to each instruction decoding operation among the computational instruction and subsequent instructions including a plurality of instructions that are sequentially arranged as an instruction sequence after the computational instruction;
and
an instruction overriding control circuit for controlling an overriding of any instruction of the subsequent instructions, the overriding of any instruction designated in response to a value of a status flag determined by execution of the computational instruction and the conditional execution status updated by the sequencer.

3 more elements

A data processing device programmed for reading in and executing instructions in a certain sequence, the data processing device comprising:

a fetch portion for reading in a computational instruction;
a decoding portion for decoding the computational instruction that has been read in;
an execution portion for executing the computational instruction in accordance with a decoding of the computational instruction;
a sequencer for updating an output to one of at least three different states as a conditional execution status in response to each instruction decoding operation among the computational instruction and subsequent instructions including a plurality of instructions that are sequentially arranged as an instruction sequence after the computational instruction;
and
an instruction overriding control circuit for overriding at least one instruction of the subsequent instructions, the at least one instruction designated in response to a value of a status flag determined by execution of the computational instruction and the conditional execution status updated by the sequencer.

3 more elements

A data processing device programmed for reading in and executing instructions in a certain sequence, the data processing device comprising:

a fetch portion for reading in a computational instruction;
a decoding portion for decoding the computational instruction that has been read in;
an execution portion for executing the computational instruction in accordance with a decoding of the computational instruction;
a sequencer for updating an output to one of at least three different states as a conditional execution status in response to each instruction decoding operation among the computational instruction and subsequent instructions including a plurality of instructions that are sequentially arranged as an instruction sequence after the computational instruction;
and
an instruction overriding control circuit for overriding at least one instruction of the subsequent instructions, the at least one instruction designated in response to a value of a status flag determined by execution of the computational instruction and the conditional execution status updated by the sequencer by allowing the fetch portion to skip reading in the at least one instruction.

3 more elements

Dependencies are inferred from the claim text.

Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer

Life of this patent

Data processing device that controls an overriding of a subsequent instruction in accordance with a conditional execution status updated by a sequencer

Life of this patent

Abstract

Claims18