Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution

A system for generating complex conditions comprising:

• an arithmetic unit which receives at least two operands from a register file;
• instruction control lines derived from a registered instruction in a processor pipeline, the instruction control lines including conditional execution control lines to control conditional operation as specified in an instruction;
• the arithmetic unit producing a result and a latched arithmetic scalar condition state;
• a first latch for holding the arithmetic scalar condition state for the instruction after the instruction has finished its execution state;
• a second latch connected to the conditional execution control lines for holding instruction control signals for the instruction after the instruction has finished its execution state;
• an arithmetic condition flag (ACF) generation unit for providing a present selected state of a plurality of arithmetic condition flags (ACFs);
• and
• an ACF latch for storing a previous state for the ACFs and feeding the previous state back to the ACF generation unit.

A processing system comprising:

• an arithmetic unit receiving at least two operands from a register file, performing an operation on the at least two operands, and producing a result and an arithmetic scalar condition state;
• conditional execution control signals derived from an instruction in an instruction pipeline to control conditional operation as specified in the instruction;
• an arithmetic condition flag (ACF) generation unit for receiving both the conditional execution control signals and the arithmetic scalar condition state, and for providing a present selected state of a plurality of arithmetic condition flags (ACFs);
• and
• a storage unit for storing a previous state of the ACFs and for feeding the previous state back to the ACF generation unit.