Methods and apparatus for memory map generation on a programmable chip

A computer system for implementing a programmable chip, the computer system comprising:

• an input interface configured to receive information identifying a first master component to be implemented on a programmable chip and information identifying a first slave component to be implemented on the programmable chip, the first slave component configurable as a component connected to the first master component;
• a storage mechanism configured to hold information for implementing a plurality of components including the first slave component, wherein information for implementing the plurality of components is included in a library of components;
• and
• a processor configured to determine a first address span for the first slave component, the first address span corresponding to a first base address and a first end address within a first valid address range associated with the first master component, wherein the first mast component is associated with a map having information identifying a valid address range and available addresses.

An apparatus for generating a memory map associated with a programmable chip, the apparatus comprising:

• means for receiving information identifying a first master component to be implemented on a programmable chip, wherein the first master component is associated with a map having information identifying a valid address range and available addresses;
• means for receiving information identifying a first slave component to be implemented on the pro ble chip, the first slave component configurable as a component connected to the first master component, wherein information for implementing the first slave component on the programmable chip is included in a library of components, wherein the library of components is provided as a database of preconfigured intellectual property components;
• means for receiving information identifying a second slave component for implementation on the programmable chip, the second slave component associated with a second address span, the second slave component configurable as a component connected to the first master component;
• means for determining a first address span for the first slave component, the first address span corresponding to a first base address and a first end address within the first valid address range;
• and
• means for determining a second address span for the second slave component, the second address span not overlapping with the first address span, wherein the second address span corresponds to a second base address and a second end address within the first valid address range.

A computer readable medium comprising computer code for implementing a programmable chip, the computer readable medium comprising:

• computer code for receiving information identifying a first master component to be implemented on a programmable chip wherein the first master component is associated with a map having information identifying a valid address range and available addresses;
• computer code for receiving information identifying a first slave component to be implemented on the programmable chip, the first slave component configurable as a component connected to the first master component, wherein information for implementing the first slave component on the programmable chip is included in a library of components, wherein the library of components is provided as a database of preconfigured intellectual property functions;
• computer code for receiving information identifying a second slave component for implementation on the programmable chip, the second slave component associated with a second address span, the second slave component configurable as a component connected to the first master component;
• computer code for determining a first address span for the first slave component, the first address span corresponding to a first base address and a first end address within the first valid address range;
• and
• computer code for determining a second address span for the second slave component, the second address span not overlapping with the first address span, wherein the second address span corresponds to a second base address and a second end address within the first valid address range.