Method and apparatus for decompressing relative addresses

An apparatus comprising:

• a storage medium having a first location to store at least a first micro-operation and an M-bit representation of an N-bit address, M being less than N, the M-bit representation having a first J-bit field;
• and
• decompression logic coupled with said storage medium to access the M-bit representation of the N-bit address and to reconstruct the N-bit address by combining at least a first portion of an instruction pointer address for the first location and the M-bit representation of the N-bit address, wherein said combining comprises adjusting the first portion of the instruction pointer address according to the value of the first J-bit field and the value of a second J-bit field of the instruction pointer address and wherein the first portion of the instruction pointer address is adjusted according to the value of a carry or borrow of a difference from the first J-bit field and the second J-bit field.

An apparatus comprising:

• a storage medium having a storage location to store a compact representation of a relative address computed with respect to a first instruction pointer address, and to associate with a second instruction pointer address different from the first instruction pointer address;
• decompression logic coupled with the storage medium to access the storage location and to reconstruct the relative address from the compact representation and a portion of the second instruction pointer address.

An apparatus comprising:

• a storage medium having a storage location to store a compact representation of a relative address computed with respect to a first instruction pointer address, and to associate with a second instruction pointer address different from the first instruction pointer address;
• decompression logic coupled with the storage medium to access the storage location and to reconstruct the relative address from the compact representation and a portion of the second instruction pointer address, wherein said reconstruction comprises adjusting the portion of the second instruction pointer address according to the values of a first field of most significant bits of the compact representation and a second field of bits of the second instruction pointer address by adding a difference from the first field and the second field to the portion of the second instruction pointer address.

An apparatus comprising:

• a storage medium having a storage location to store a compact representation of a relative address computed with respect to a first instruction pointer address, and to associate with a second instruction pointer address different from the first instruction pointer address;
• decompression logic coupled with the storage medium to access the storage location and to reconstruct the relative address from the compact representation and a portion of the second instruction pointer address, wherein said reconstruction comprises adjusting the portion of the second instruction pointer address according to the values of a first field of most significant bits of the compact representation and a second field of bits of the second instruction pointer address and wherein the portion of the second instruction pointer address is adjusted according to the value of a carry or borrow of a difference from the first field and the second field.