Configurable address generator and circuit using same
AssigneeXilinx, Inc.
InventorsJonathan B. Ballagh, Eric R. Keller, Roger B. Milne
Life of this patent
Estimating the term…
Abstract
A configurable address generator includes addressing sequence circuitry such as a set of counters. A set of comparators is also preferably included in the configurable address generator in order to detect different addressing conditions (e.g., full, empty, etc.). Coupled to these components is a plurality of programmable bits that allows the address generator to be configured to meet a number of different design requirements. For example, the configurable address generator can be configured as a stack pointer; it can also be configured to provide address generation for FIFO and MAC-based filter circuits, etc.
Claims22
A configurable address generation circuit, comprising:
- an addressing sequence circuit comprising a plurality of counting circuits and at least one comparator coupled to the plurality of counting circuits;
- and
- programmable logic coupled to the addressing sequence circuit, the programmable logic configuring the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the configurable address generation circuit to meet one of a plurality of address generation requirements, the programmable logic being programmed so that the configurable address generation circuit provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses.
An integrated circuit, comprising:
- an addressing sequence circuit comprising a plurality of counting circuits and a comparator coupled to the plurality of counting circuits;
- programmable logic coupled to the addressing sequence circuit, the programmable logic used to configure the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the integrated circuit, the programmable logic being programmed so that the integrated circuit provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses;
- and
- a memory coupled to the addressing sequence circuit.
A Field Programmable Gate Array (FPGA), comprising:
- an addressing sequence circuit comprising a plurality of counting circuits and a comparator coupled to the plurality of counting circuits;
- and
- programmable logic coupled to the addressing sequence circuit, the programmable logic configuring the addressing sequence circuit in response to proarammable bits of a configuration bit file coupled to the FPGA in order to provide addressing to different types of circuits, the proarammable logic being programmed so that the FPGA provides address generation wherein a first counting circuit of the plurality of counting circuits provides write addresses and a second counting circuit of the plurality of counting circuits provides read addresses.
An integrated circuit, comprising:
- an addressing sequence circuit, comprising a means for counting and a means for comparing;
- and
- a means for configuring the addressing sequence circuit in response to programmable bits of a configuration bit file coupled to the integrated circuit in order to provide addressing to different types of circuits, the means for configuring being programmed so that the integrated circuit provides address generation wherein a first counting circuit of the means for counting provides write addresses and a second counting circuit of the means for counting circuits provides read addresses.
Dependencies are inferred from the claim text.