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US 7,010,658 B2Granted
Transceiver with latency alignment circuitry
AssigneeRambus Inc.
InventorsKevin Donnelly, Mark Johnson, Chanh Tran
Life of this patent
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Abstract
In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
Claims32
A transceiver, comprising:
- a first interface configured to receive data from a first channel using a first clock signal and to transmit data to the first channel using a second clock signal;
- a second interface configured to receive data from a second channel using a third clock signal and to transmit data to the second channel using a fourth clock signal;
- and
- a re-timer configured to re-time data received from the first channel using the first clock signal and to retransmit the data to the second channel using the fourth clock signal.
1 more element
A system comprising:
- a first channel;
- a second channel;
- a first device coupled to the first channel;
- a second device coupled to the second channel;
- and
- a transceiver having latency aligning circuitry coupled to the first channel and to the second channel,
- wherein the latency aligning circuitry includes a re-timer to re-time data received from the first channel using a first clock signal and to retransmit the data to the second channel using a second clock signal.
4 more elements
A system comprising:
- a first channel;
- a second channel;
- a first device coupled to the first channel;
- a second device coupled to the second channel;
- and
- a transceiver having latency aligning circuitry coupled to the first channel and to the second channel;
- wherein data transmissions from the first device to the first channel are clocked by a first clock signal and wherein the latency aligning circuitry aligns the round-trip latency between the first device and the second channel to an integer number of cycles of the first clock signal.
4 more elements
A system comprising:
- a first channel;
- a second channel;
- a first device coupled to the first channel;
- a second device coupled to the second channel;
- and
- a transceiver having latency aligning circuitry coupled to the first channel and to the second channel;
- wherein the system has a round trip latency from the first device to the second device that is independent of a flight time from the first device to the transceiver.
4 more elements
A memory system comprising
- a memory controller coupled to a primary channel;
- a first transceiver, having latency aligning circuitry, coupled to the primary channel and to a first stick channel;
- a first memory device having a programmable delay coupled to the first stick channel;
- and
- a second memory device having a programmable delay coupled to the primary channel or the first stick channel,
- wherein the latency aligning circuitry includes a re-timer to re-time data received from the primary channel using a first clock signal and to retransmit the data to the first stick channel using a second clock signal.
3 more elements
A memory system comprising
- a memory controller coupled to a primary channel;
- a first transceiver, having latency aligning circuitry, coupled to the primary channel and to a first stick channel,
- a first memory device having a programmable delay coupled to the first stick channel;
- and
- a second memory device having a programmable delay coupled to the primary channel or the first stick channel;
- wherein the latency aligning circuitry of the first and second transceivers aligns a respective round-trip latency between the memory controller and each of the transceivers to a respective integer number of clock cycles.
3 more elements
Dependencies are inferred from the claim text.