Method and apparatus for avoiding cache pollution due to speculative memory load operations in a microprocessor

A microprocessor system for avoiding cache pollution comprising:

• a dependency checker for determining a dependency state condition between a first load instruction and a second load instruction;
• an instruction scheduler coupled to said dependency checker, said instruction scheduler having an instruction buffer storing said first load instruction and said second load instruction, said instruction scheduler scheduling execution of said first load instruction and said second load instruction;
• an execution unit coupled to said instruction scheduler;
• a cache system having a cache memory and coupled to said execution unit, said cache system having a cache miss state condition output for a cache miss state condition in said cache memory for said first load instruction;
• a cache pollution avoidance unit coupled to said cache system and coupled to said dependency checker said cache pollution avoidance unit comprising:
• a dynamic memory dependency table storing said dependency state condition between said first load instruction and said second load instruction;
• a cache miss identification (ID) decode unit having a cache miss ID decode input coupled to said cache miss state condition output of said cache system and having a cache miss ID decode output;
• a logical combining gate having a gate first input coupled to said dependency state condition between said first load instruction and said second load instruction stored in said dynamic memory dependency table, said logical combining gate having a gate second input coupled to said cache miss ID decode output of said cache miss ID decode unit, said logical combining gate having a gate output;
• and
• wherein said instruction scheduler squashes execution by said execution unit of said second load instruction stored in said instruction buffer whenever said output of said logical combining gate is true.