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US 7,010,632 B2Granted
Operating memory components
AssigneeNokia Corporation
InventorMatti Floman
Life of this patent
Estimating the term…
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AssigneeNokia Corporation
InventorMatti Floman
Estimating the term…
A hardware unit (2) for operating memory components comprises a memory controller, a bus and a plurality of interface pins 3–6. The bus is connected to the memory controller and to the interface pins. In order to enable a flexible employment of the hardware unit, the memory controller determines the number of memory components (21,31,41,42,51,52,61,62) connected to the interface pins. In case at least one memory component is determined, the memory controller divides the capacity of the bus into as many portions as there are connected memory components, allocates each portion to another group of interface pins to which a separate memory component is connected, and exchanges signals via the bus and the interface pins separately with each connected memory component. The invention relates equally to an electronic device 1 comprising such a hardware unit and to a corresponding method.
A hardware unit (2) for operating memory components, which hardware unit (2) comprises a memory controller, a plurality of interface pins (3–6) and a bus connected to said memory controller and to said interface pins (3–6), said memory controller determines the number of memory components (21,31,41,42,51,52,61,62) external to said hardware unit (2) and connected to said interface pins (3–6), wherein in case at least one memory component (21,31,41,42,51,52,61,62) is determined to be connected to said interface pins (3–6), said memory controller divides the capacity of said bus into as many portions as there are connected memory components (21,31,41,42,51,52,61,62), allocates each portion to another group of said interface pins (3–6) to which a separate memory component (21,31,41,42,51,52,61,62) is connected, and exchanges signals via said bus and said interface pins (3–6) separately with each connected memory component (21,31,41,42,51, 52,61,62).
A method for operating memory components (21,31,41,42,51, 52,61,62) connected to interface pins (3–6) of a hardware unit (2), which hardware unit (2) further comprises a memory controller and a bus connected to said memory controller and to said interface pins (3–6), said method comprising:
Dependencies are inferred from the claim text.