DMA prefetch
AssigneeInternational Business Machines Corporation
InventorJames Allan Kahle
Life of this patent
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Abstract
A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a processor. A load access pattern of the DMA mechanism is detected. At least one potential load of data is predicted based on the load access pattern. In response to the prediction, the data is prefetched from a system memory to a cache before a DMA command requests the data.
Claims21
A method for prefetching data from a system memory to a cache for a direct memory access (DMA) in a multi-processor computer system having a plurality of processor complexes (PCs) and at least one processing unit, wherein each PC comprises a processor unit (PU) coupled to a local store and a memory flow controller (MFC), the method comprising the steps of:
- coupling the cache to each MFC and the system memory such that the cache interfaces all PCs to each other and each PC to the system memory;
- requesting, by a first MFC in a first PC, data from the system memory to be transferred to a first local store for processing by a first PU;
- detecting a load access pattern of the data by the first MFC;
- predicting at least one potential load of data based on the load access pattern;
- in response to the prediction, prefetching the potential load of data from the system memory to the cache before a DMA command requests the potential load of data;
- and
- in response to any one of the plurality of MFCs issuing a DMA command request for the potential load of data, fetching the potential load of data directly from the cache to the local store coupled to the issuing MFC without accessing system memory.
An apparatus for prefetching data from a system memory to a cache for direct memory access (DMA) in a multi-processor computer system having a plurality of processor complexes (PCs) and at least one processing unit, wherein each PC comprises a processor unit (PU) coupled to a local store and a memory flow controller (MFC), the apparatus comprising:
- means for coupling the cache to each MFC and the system memory such that the cache interfaces all PCs to each other and each PC to the system memory;
- means for requesting, by a first MFC in a first PC, data from the system memory to be transferred to a first local store for processing by a first PU;
- means for detecting a load access pattern of the data by the first MFC;
- means for predicting at least one potential load of data based on the load access pattern;
- means for, in response to the prediction, prefetching the potential load of data from the system memory to the cache before a DMA command requests the potential load of data;
- and
- means for, in response to any one of the plurality of MFCs issuing a DMA command request for the potential load of data, fetching the potential load of data directly from the cache to the local store coupled to the issuing MFC without accessing system memory.
A computer program product for prefetching data from a system memory to a cache for a direct memory access (DMA) in a multi-processor computer system having a plurality of processor complexes (PCs) and at least one processing unit, wherein each PC comprises a processor unit (PU) coupled to a local store and a memory flow controller (MFC), the computer program product comprising:
- computer program code for coupling the cache to each MFC and the system memory such that the cache interfaces all PCs to each other and each PC to the system memory;
- computer program code for requesting, by a first MFC in a first PC, data from the system memory to be transferred to a first local store for processing by a first PU;
- computer program code for detecting a load access pattern of the data by the first MFC;
- computer program code for predicting at least one potential load of data based on the load access pattern;
- computer program code for in response to the prediction, prefetching the potential load of data from the system memory to the cache before a DMA command requests the potential load of data;
- and
- computer program code for, in response to any one of the plurality of MFCs issuing a DMA command request for the potential load of data, fetching the potential load of data directly from the cache to the local store coupled to the issuing MFC without accessing system memory.
Dependencies are inferred from the claim text.