Universal serializer/deserializer
AssigneeUbicom, Inc.
InventorsKwok Hung Si, Tibet Mimaroglu
Life of this patent
Estimating the term…
Abstract
A universal serializer/deserializer (“ser/des”) is disclosed that provides hardware implemented modules of those functions determined to be most applicable to a communications protocol. Functionality that is determined to be more unique for a given protocol is implemented in software. Accordingly, a universal ser/des is provided that is able to be used for a plurality of different protocols now known, and configured to communicate with protocols that may be developed in the future.
Claims33
A deserializer for receiving data transmitted over a network, the deserializer in a universal serializer/deserializer programmable for implementing two or more communications protocols, the deserializer comprising:
- a programmable receive data circuit for receiving the data, for performing initial data receive functions, and for coupling to a network connection;
- a synchronization circuit for selectably detecting a synchronization pattern in the data, the synchronization circuit configured to be programmed with the synchronization pattern corresponding to a current protocol of the two or more communications protocols, and coupled to the programmable receive data circuit for signaling a match signal in response to matching the synchronization pattern with the data;
- a selectable CRC circuit for detecting errors in the data and determining integrity of the data, the selectable CRC circuit coupled to the programmable receive data circuit for signaling in response to detecting an error or in the data;
- a data storage device for storing the data to be accessed by a CPU, the data storage device coupled to the programmable receive data circuit for receiving the data;
- and
- an interrupt generator for generating interrupt signals in response to interrupt generating signals, the interrupt generator coupled to the programmable receive data circuit, the selectable CRC circuit, the synchronization circuit, and the data storage device for receiving the interrupt generating signals, and coupled to the CPU for providing the interrupt signals.
A data receive circuit for a deserializer in a universal programmable serializer/deserializer having a synchronization circuit, a data storage device and a CRC circuit for implementing a programmed protocol from a set of communications protocols, the data receive circuit comprising:
- an exclusive-OR gate (XOR) configurable to be coupled to a network connection for receiving an input signal carrying a data and for selectably performing a polarity inversion of the input signal;
- a polarity inverter coupled to the XOR for inverting the input signal and configured to receive a first program signal indicating whether the programmed protocol requires the polarity inversion;
- a clock detection and configuration circuit coupled to the XOR for detecting a protocol specific start condition of the programmed protocol selected from a set of programmed start condition patterns and for providing a protocol specific clock signal of the programmed protocol selected from a set of programmed clock signal definitions in response to receiving a protocol selection indicating the programmed protocol;
- a clock/data separation circuit coupled to the clock detection and configuration circuit for selectably providing separation of clock information from data information in the input signal in response to receiving the protocol selection indicating the programmed protocol;
- a decoder coupled to the clock/data separation circuit for selectably performing a protocol specific decoding function of the programmed protocol selected from a set of programmed decoding functions in response to receiving the protocol selection indicating the programmed protocol;
- a multiplexer coupled to the clock detection and configuration circuit, to the clock/data separation circuit, and to the decoder for supplying the protocol selection and configured to receive a second program signal indicating the requirements of the programmed protocol;
- a receive shift register coupled to the decoder, to the synchronization circuit, to the CRC circuit and to the data storage device, the receive shift register for receiving the data one bit at a time from the decoder and providing the data, several bits at a time, to the synchronization circuit, the CRC circuit, and the data storage device;
- a control logic circuit coupled to the receive shift register, and the synchronization circuit, the control logic for receiving a synchronization match signal from the synchronization circuit and for instructing the receive shift register to provide the data to one of the synchronization device and the data storage device and for setting a number of bits in the several bits used in accordance to the programmed protocol in response to a third program signal indicating the number of bits required by the programmed protocol.
A synchronization circuit for a deserializer in a universal programmable serializer/deserializer having a data receive circuit, the serializer/deserializer for implementing a programmed protocol from a set of communications protocols, the synchronization circuit comprising:
- a synchronization register configured to receive a first program signal indicating a synchronization pattern corresponding to the programmed protocol;
- a programmable synchronization mask coupled to the synchronization register through as set of logic gates for masking out a corrupted bit for optimizing the synchronization circuit to operate in a particular environment, the programmable synchronization mask configured to receive a program signal indicating settings for the masking;
- and
- a comparator coupled to the programmable receive data circuit for receiving an input data signal and coupled to the logic gates for receiving the synchronization pattern, the comparator for comparing the synchronization pattern with the input data signal and for producing a match signal in response to matching the synchronization pattern with the input data signal.
A serializer for transmitting data over a network, the serializer in a universal serializer/deserializer programmable for implementing two or more communications protocols, the serializer comprising:
- a data buffer for receiving the data to be transmitted from a processor and configured to receive a load signal for loading off the data;
- a transmit shift register coupled to the data buffer for loading the data off the data buffer, the shift register further for serially shifting the data out;
- a control logic circuit coupled to the data buffer for providing the load signal and configured to receive a bit number corresponding the a current protocol of the two or more communications protocols, wherein the load signal is provided upon reaching a bit-number number of bits received by the data buffer;
- and
- a programmable encoder coupled to the transmit shift register for receiving the shifted out data, for selectably performing an encoding function required for the current protocol in response to receiving a protocol selection signal indicating the current protocol, and for transmitting the data out of the serializer.
Dependencies are inferred from the claim text.