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US 7,010,563 B2Granted
Multiplier with output current scaling
AssigneeIntel Corporation
InventorsDavid J. Comer, Aaron K. Martin, James E. Jaussi
Life of this patent
Estimating the term…
Abstract
A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.
Claims30
A circuit comprising:
- an input stage to produce a first current at a first source node and a second current at a second source node;
- a plurality of output transistors connected between the first and second source nodes and a first summing node and a second summing node to pass a first portion of the first current and a first portion of the second current to the first and second summing nodes;
- and
- a plurality of scaling transistors connected between the first and second source nodes and a reference node to pass a second portion of the first current and a second portion of the second current to the reference node, wherein each of the output transistors includes a first channel width to channel length ratio, wherein each of the scaling transistors includes a second channel width to channel length ratio, and wherein the first channel width to channel length ratio is different from the second channel width to channel length ratio.
1 more element
A circuit comprising:
- an input stage to produce a first current at a first source node and a second current at a second source node;
- a plurality of output transistors connected between the first and second source nodes and a first summing node and a second summing node to pass a first portion of the first current and a first portion of the second current to the first and second summing nodes;
- and
- a plurality of scaling transistors connected between the first and second source nodes and a reference node to pass a second portion of the first current and a second portion of the second current to the reference node;
- and
- a current reduction unit connected between the first and second source nodes to subtract a DC current from the input stage.
3 more elements
A circuit comprising:
- an input stage to produce a first current at a first source node and a second current at a second source node;
- a plurality of output transistors connected between the first and second source nodes and a first summing node and a second summing node to pass a first portion of the first current and a first portion of the second current to the first and second summing nodes;
- and
- a plurality of scaling transistors connected between the first and second source nodes and a reference node to pass a second portion of the first current and a second portion of the second current to the reference node, wherein each of the output transistors includes a first channel width, and each of the scaling transistors includes a second channel width, wherein the second channel width is a multiple of the first channel width.
1 more element
A circuit comprising:
- an input stage to source a first current to a first source node and a second current to a second source node;
- a first summing path connected to the first and second source nodes to pass a first portion of the first current and a first portion of the second current to a first summing node;
- a second summing path connected to the first and second source nodes to pass a second portion of the first current and a second portion of the second current to a second summing node, each of the first and second summing paths including a plurality of output transistors;
- a first current-diverting path connected to the first source node to pass a third portion of the first current to a reference node;
- and
- a second current-diverting path connected to the second source node to pass a third portion of the second current to the reference node, each of the first and second current-diverting paths including a plurality of scaling transistors.
3 more elements
A circuit comprising:
- an input stage including a first input transistor and a second input transistor;
- a first output transistor connected between the first input transistor and a first summing node, and a second output transistor connected between the second input transistor and the first summing node;
- a third output transistor connected between the first input transistor and a second summing node, and a fourth output transistor connected between the second input transistor and the second summing node, the first, second, third, and fourth output transistors having a first channel width;
- and
- a first scaling transistor and a second scaling transistor, each being connected between the first input transistor and a reference node, and a third scaling transistor and a fourth scaling transistor, each being connected between the second output transistor and the reference node, the first, second, third, and fourth scaling transistors having a second channel width, wherein the second channel width and the first channel width are unequal.
2 more elements
An integrated circuit comprising:
- a plurality of multipliers to receive a plurality of multiplier input signals;
- and
- a summing circuit connected to the multipliers to sum currents at a first summing node and a second summing node, wherein each of the multiplier includes:
- an input stage connected to a first source node and a second source node;
- and
- a plurality of transistor pairs connected to the first and second source nodes, wherein each of the transistor pairs includes transistors having unequal channel width to channel length ratios and having a common source connected to one of the first and second source nodes.
3 more elements
A system comprising:
- a transmitter;
- a point-to-point transmission medium connected to the transmitter to transmit a plurality of transmitted signals;
- and
- a receiver connected to the point-to-point transmission medium to receive the transmitted signals and produce a plurality of sampled signals, the receiver including:
- a plurality of multipliers to receive the plurality of sampled signals and a plurality of code input signals;
- and
- a summing circuit connected to the multipliers to sum currents at a first summing node and a second summing node, wherein each of the multiplier includes:
- an input stage connected to a first source node and a second source node;
- and
- a plurality of transistor pairs connected to the first and second source nodes, wherein each of the transistor pairs includes transistors having unequal channel width to channel length ratios and having a common source connected to one of the first and second source nodes.
7 more elements
A method comprising:
- producing a first current at a first source node;
- producing a second current at a second source node;
- passing a first portion of the first current and a first portion of the second current to a first summing node;
- and
- passing a second portion of the first current and a second portion of the second current to a second summing node;
- and
- passing a third portion of the first current and a third portion of the second current to a reference node.
4 more elements
Dependencies are inferred from the claim text.