Data processor with enhanced instruction execution and method

A pipelined digital processor adapted for performing iterative calculations on a plurality of data, said processor having an instruction set with at least one extension instruction, said at least one extension instruction adapted for FFT butterfly calculation, the processor comprising:

• at least one multiply-accumulate stage having at least one accumulator associated therewith;
• at least one register window;
• and
• write-back logic operatively connected to said at least one multiply-accumulate stage;
• wherein said at least one extension instruction being adapted to:
• (i) subtract a value present in said at least one accumulator from a multiple of a first one of said plurality of data;
• (ii) preload said at least one accumulator with a second one of said plurality of data;
• and
• (iii) cooperate with said logic to write back the result of said subtraction to said window register.

An extensible processor adapted for performing iterative calculations on a plurality of data, said processor having a multi-stage instruction pipeline and an extension instruction set, comprising:

• at least one multiply-accumulate apparatus having at least one accumulator associated therewith;
• at least one first extension instruction being adapted to perform at least a portion of an iterative calculation on said plurality of data;
• and
• at least one second extension instruction adapted to perform a multiply or multiply-accumulate operation using said at least one multiply accumulate apparatus and accumulator;
• wherein said at least one first extension instruction is pipelined to the same number of stages as said at least one second extension instruction, thereby avoiding pipeline stalling during processing of said at least one first instruction.

A user-extensible processor adapted for performing iterative calculations on a plurality of data, said processor having a multi-stage instruction pipeline and an extension instruction set, comprising:

• at least one multiply-accumulate apparatus having at least one accumulator associated therewith;
• at least one first extension instruction being adapted to perform at least a portion of an iterative calculation on said plurality of data;
• and
• at least one second extension instruction adapted to perform a multiply or multiply-accumulate operation using said at least one multiply accumulate apparatus and accumulator;
• wherein the propagation of said at least one first extension instruction within said pipeline is controlled at least in part through added pipeline depth, said added pipeline depth providing for reduced execution time of said at least one first extension instruction.

A method of performing an iterative calculation using a user-configurable, extensible processor having an instruction set, pipeline, and at least one multiply-accumulate apparatus with accumulator, the method comprising:

• inserting a first extension instruction into said pipeline, said first instruction adapted to:
• (i) subtract a value present in said at least one accumulator from a multiple of a first input value;
• (ii) preload said at least one accumulator with a second input value;
• and
• (iii) write back the result of the aforementioned subtraction operation to a designated register location;
• providing a plurality of inputs to said at least one multiply-accumulate apparatus said plurality of inputs comprising at least said first and second inputs;
• and
• executing said first extension instruction to produce at least one output from said at least one multiply-accumulate apparatus.

A method of configuring a processor to perform an iterative calculation, said processor having an instruction set, pipeline, and at least one multiply-accumulate apparatus, said method comprising:

• synthesizing said processor at least in part using the method comprising:
• (i) providing a first extension instruction in a hardware description language (HDL), said first extension instruction being adapted to utilize existing logic within said processor related to other instructions within said instruction set,
• (ii) adding said first extension instruction to the design of extended data processor;
• and
• (iii) synthesizing the extended processor design including said first extension instruction, said first extension instruction being pipelined to the same number of stages as at least one of said other instructions;
• and
• inserting said first extension instruction into said pipeline;
• providing a plurality of inputs to said at least one multiply-accumulate apparatus;
• and
• executing said first extension instruction to produce at least one output from said at least one multiply-accumulate apparatus.

An integrated circuit device optimized for performing iterative calculations on input data, comprising:

• at least one silicon die having a plurality of circuit features formed thereon;
• and
• an extended processor having a multi-stage instruction pipeline and an extension instruction set, comprising:
• at least one multiply-accumulate apparatus having at least one accumulator associated therewith;
• at least one first extension instruction being adapted to perform at least a portion of an iterative calculation on said plurality of data;
• and
• at least one second extension instruction adapted to perform a multiply or multiply-accumulate operation using said at least one multiply accumulate apparatus and accumulator;
• wherein said at least one first extension instruction is pipelined to the same number of stages as said at least one second extension instruction, thereby avoiding pipeline stalling during processing of said at least one first instruction.

A digital processor adapted for performing iterative calculations, comprising:

• a multistage instruction pipeline;
• and
• an accumulator in signal communication with said pipeline, said accumulator comprising:
• an adder having first and second inputs, said second input being operatively coupled to a first multiplier, said adder adapted to add said inputs to produce at least one output;
• a first multiplexer adapted to multiplex a plurality of inputs onto at least one output;
• at least one of said plurality of inputs comprising at least one of said at least one outputs of said adder, at least one of said plurality of inputs of said first multiplexer comprising a pre-load signal associated with a butterfly operation;
• and
• at least one register operatively coupled to said at least one output of said first multiplexer and said first input of said adder.

A user-configured and extended pipelined processor adapted for performing iterative calculations on a plurality of data, said processor having an extension instruction set associated therewith, and comprising:

• at least one multiply-accumulate apparatus having at least one accumulator associated therewith;
• at least one register window;
• at least one extension instruction provided within said extension instruction set, said at least one extension instruction being adapted to:
• (i) subtract a value present in said at least one accumulator from a multiple of a first one of said plurality of data;
• and
• (ii) preload said at least one accumulator with a second one of said plurality of data;
• and
• logic operatively connected to said at least one multiply-accumulate apparatus and adapted to write back the result of said subtraction to said register window.

A user-configured and user-extended pipelined processor adapted for performing FFT butterfly calculations on a plurality of data, said processor having a base instruction set and an extension instruction set associated therewith, said processor comprising:

• at least one dual 16-bit multiply-accumulate apparatus having at least one accumulator associated therewith;
• at least one register window;
• and
• at least one extension instruction included within said extension instruction set based on a selection thereof by said user, said at least one extension instruction being adapted to:
• subtract a value present in said at least one accumulator from a multiple of a first one of said plurality of data;
• and
• preload said at least one accumulator with a second one of said plurality of data;
• wherein said FFT butterfly calculation comprises three machine cycles.