Event pipeline and summing method and apparatus for event based test system
AssigneeAdvantest Corporation
InventorsGlen Gomes, Anthony Le
Life of this patent
Estimating the term…
Abstract
An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.
Claims19
An event pipeline and summing apparatus for processing event data stored in an event memory of an event based test system, comprising:
- an event count delay logic which produces a gross delay of event count data, which is an integral part of the event data, by counting a clock by a number of times defined by the event count data;
- a vernier data decompression logic which reproduces event vernier data which is a fractional part of the event data;
- an event vernier summing logic which produces event vernier sum data by summing the vernier data from the vernier data decompression logic;
- and
- an event scaling logic which changes the event count data from the event count delay logic and the event vernier data from the event vernier summing logic in proportion to a scale factor;
- wherein a plurality of parallel pipelines are incorporated at least in the event vernier summing logic for processing the event vernier data in parallel where each pipeline is configured by a plurality of series connected registers.
An event pipeline and summing method for processing event data stored in an event memory of an event based test system, comprising the following steps of:
- producing a gross delay of event count data, which is an integral part of the event data from the event memory, by counting a clock by a number of times defined by the event count data;
- decompressing event vernier data which is a fractional part of the event data in the event memory;
- summing the event vernier data based on the decompressed event vernier data through a plurality of pipelines arranged in parallel and shifting the event vernier data at each timing of the clock to produce event vernier sum data where each pipeline is configured by a plurality of series connected registers;
- and
- modifying the event count data and the event vernier data in proportion to a scale factor.
Dependencies are inferred from the claim text.