Gated clock recovery circuit

A method for recovering a clock signal from an incoming data stream, comprising:

• tuning a first phase-locked loop (PLL) circuit to a local clock signal operating at substantially the same frequency as a transmitter clock, wherein said first PLL circuit produces a bias signal;
• applying said bias signal to a second PLL circuit in a first mode, said second PLL circuit generating a clock output signal in said first mode having a frequency determined by said bias signal;
• and
• removing said bias signal from said second PLL circuit in a second mode, wherein said second PLL circuit has an initial frequency in said second mode determined by said bias signal and whereby said second PLL substantially instantaneously adjusts said clock output signal to phase changes in said incoming data stream in said second mode.

A clock recovery circuit, comprising:

• first means for generating a first oscillator signal having substantially the same frequency as a transmitter clock;
• means for generating a bias signal;
• second means for generating a clock output signal having an initial frequency determined by said bias signal and substantially instantaneously adjusting said clock signal output signal to phase changes of data in an input data stream without utilizing said bias signal;
• and
• means for selectively imposing said bias signal from said first means to said second means.

A clock recovery circuit, comprising:

• a first phase-locked loop (PLL) circuit for generating an oscillator signal having substantially the same frequency as a transmitter clock and for generating a bias signal;
• a second PLL circuit generating a clock output signal in accordance with a control input;
• a phase detector for generating an error signal indicating a difference in phase between an incoming reference signal and said clock output signal;
• and
• a switch for selecting one of said bias signal and said incoming reference signal to generate said control input.