Aligned clock forwarding scheme
AssigneeSilicon Integrated Systems Corp.
InventorsMing-Hsien Lee, Tsan-Hui Chen
Life of this patent
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Abstract
An aligned clock forwarding scheme of an electronic system includes a first circuit path generating an aligned clock output signal to a subsystem and a second circuit path generating an aligned data signal to the subsystem. An external clock input serves as the source of the clock signal for the aligned clock forwarding scheme. A multiplication circuit receives the external clock input and sends multiplied clock signals to control the first and second circuit paths. The two circuit paths have the same physical characteristics so that both clock output and data signals experience the same environmental effect. There is no additional skew incurred between the clock and data signals during the data transfer between the two subsystems.
Claims10
A circuit for generating aligned clock and data signals, comprising:
- a clock input;
- a clock multiplication circuit for receiving an external clock signal from said clock input and generating a multiplied clock signal;
- a first circuit path receiving said external clock signal and said multiplied clock signal and generating an aligned clock signal;
- and
- a second circuit path receiving said multiplied clock signal and generating an aligned data signal;
- wherein said first and second circuit paths comprise identical circuit components, and said aligned clock signal generated by said first circuit path serves as a clock signal for said aligned data signal generated by said second circuit path.
A circuit for generating aligned clock and data signals, comprising:
- a clock input;
- an inverter receiving an external clock signal from said clock input and generating an inverted clock signal;
- a clock multiplication circuit receiving said external clock signal and generating a multiplied clock signal and an inverted multiplied clock signal;
- a first circuit path receiving said inverted clock signal and said inverted multiplied clock signal, and generating an aligned clock signal;
- and
- a second circuit path receiving said multiplied clock signal and generating an aligned data signal;
- wherein said first and second circuit paths comprise identical circuit components, and said aligned clock signal generated by said first circuit path serves as a clock signal for said aligned data signal generated by said second circuit path.
A circuit for generating aligned clock and data signals, comprising:
- a clock input;
- an inverter receiving an external clock signal from said clock input and generating an inverted clock signal;
- a clock multiplication circuit receiving said external clock signal and generating a multiplied clock signal and an inverted multiplied clock signal;
- a first circuit path receiving said inverted clock signal and said inverted multiplied clock signal, and generating an aligned clock signal;
- a second circuit path receiving said inverted multiplied clock signal and generating an aligned data strobe signal;
- a third circuit path receiving said multiplied clock signal and generating an aligned first data signal;
- and
- a fourth circuit path receiving said multiplied clock signal and generating an aligned second data signal;
- wherein said first, second, third and fourth circuit paths comprise identical circuit components, said aligned clock signal serves as a clock signal for said aligned first data signal and said aligned second data signal, and said aligned data strobe signal serves as a data strobe signal for said aligned first data signal and said aligned second data signal.
Dependencies are inferred from the claim text.