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US 7,009,964 B2Granted
Rotator switch data path structures
AssigneeNortel Networks Limited
InventorsDavid Anthony Fisher, Michel Langevin
Life of this patent
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Abstract
Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing from/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.
Claims19
A switch comprising
- a first commutator cyclically connecting each source node from among a first number of source nodes to each intermediate memory device from among a second number of independent intermediate memory devices;
- and
- a second commutator cyclically connecting said each intermediate memory device to each output port from among a third number of second-commutator output ports;
- wherein
- at least one of said first commutator input ports is time-shared by at least two source nodes from among said first number of source nodes, said first number being determined according to the speed of said intermediate memory device relative to the speed of said source node.
2 more elements
A method of switching comprising:
- determining a speed of a plurality of intermediate memory devices, and a speed of plurality of source nodes;
- multiplexing at least two source nodes into a multiplexed input;
- cyclically connecting said multiplexed input to an input port of a first commutator having a plurality of input ports;
- cyclically connecting said input port to each intermediate memory device from among said plurality of intermediate memory devices;
- and
- cyclically connecting said each intermediate device to output ports of a second commutator having a plurality of second commutator output ports.
3 more elements
A switch comprising:
- a plurality of input commutators, each input commutator associated with a respective plurality of source nodes and cyclically connecting each source node from among said respective plurality of source nodes to respective output ports of said each input commutator;
- a plurality of intermediate memory devices each connecting to an output port from each input commutator of said plurality of input commutators;
- and
- a plurality of output commutators each output commutator associated with a respective plurality of destination nodes and cyclically connecting each intermediate memory device from among said plurality of intermediate memory devices to a destination node from among said respective plurality of destination nodes associated with each of said output commutators.
1 more element
Dependencies are inferred from the claim text.