Memory array decoder

A method for selecting a storage location in a memory device, comprising:

• enabling a decoder in response to at least one of an address signal and a match signal;
• generating a location select signal with said enabled decoder;
• and
• terminating said location select signal in response to said address signal and a precharge signal.

A method for accessing a memory location, comprising:

• enabling at least one of a decoder circuit and a redundant decoder circuit in response to at least one of a pre-decoded address signal, a redundant column select enable signal, and a match signal;
• generating one of a column select signal with said enabled decoder circuit and a redundant column select signal with said enabled redundant decoder circuit;
• and
• terminating said one of a column select signal and a redundant column select signal in response to a precharge signal and at least one of said pre-decoded address signal and said redundant column select enable signal.

A decoder, comprising:

• an input for receiving a first signal;
• a first node connected to said input via an enabling device which is responsive to a second signal;
• a plurality of inverters for generating a location select signal in response to said first and second signals;
• and
• a feedback loop responsive to said location select signal, said feedback loop supplying at least one of a precharge signal and a latch signal to said first node.

A column address circuit for a memory device, comprising:

• a command decode circuit operable to generate at least one of an enable signal and a precharge signal;
• an address trap circuit responsive to said command decode circuit to convert an address signal into a column address signal;
• a redundancy compare circuit responsive to said command decode circuit and said address trap circuit to generate a match signal and a redundant column select enable signal;
• an address pre-decode circuit responsive to said command decode circuit, said address trap circuit, and said redundancy compare circuit to generate a pre-decoded column address signal in response to said column address signal;
• and
• a decoder circuit operable to generate at least one of a column select signal in response to said pre-decoded column address signal and a redundant column select signal in response to said redundant column select enable signal, said decoder circuit further responsive to said precharge signal to terminate said one of a column select signal and a redundant column select signal.

A memory device, comprising:

• a memory array having a plurality of memory cells, a plurality of wordlines and a plurality of digitlines, wherein said memory cells are accessible by said wordlines and said digitlines, and a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising:
• a digitline driver for activating at least one of said digitlines, said digitline driver responsive to a decoder output signal;
• and
• a decoder for providing said decoder output signal, said decoder comprising:
• an input for receiving a first signal;
• a first node connected to said input via an enabling device which is responsive to a second signal;
• a plurality of inverters for generating said decoder output signal in response to said first and second signals;
• and
• a feedback loop responsive to said decoder output signal, said feedback loop supplying at least one of a precharge signal and a latch signal to said first node.