Semiconductor memory having a flexible dual-bank architecture with improved row decoding

A semiconductor memory comprising:

• a plurality of memory arrays each having a plurality of sectors, each sector having a plurality of memory cells arranged along rows and columns;
• reconfigurable address decode circuitry coupled to access memory cells in the plurality of memory arrays in response to row and column addresses, wherein the plurality of memory arrays are partitioned into first and second memory banks by configuring the address decode circuitry into one of a plurality of mask-selectable configurations such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays, and each of the mask-selectable configurations corresponds to one of a plurality of metal masks used to form a metal layer in the semiconductor, the address decode circuitry comprising:
• an array select predecoder configured to select a first memory array in the first memory bank in response to a first subset of a first bank address, and a second memory array in the second memory bank in response to a first subset of a second bank address;
• a first horizontal global row decoder configured to provide a first plurality of predecoded row address signals in response to a second subset of the first bank address;
• a second horizontal global row decoder configured to provide a second plurality of predecoded row address signals in response to a second subset of the second bank address;
• a plurality of horizontal local row decoders each coupled to one of the plurality of memory arrays, wherein:
• the horizontal local row decoder coupled to the selected first memory array selects a sector in the selected first memory array in response to the first plurality of predecoded row address signals, and
• the horizontal local row decoder coupled to the selected second memory array selects a sector in the selected second memory array in response to the second plurality of redecoded row address signals;
• and
• a plurality of vertical global row decoders each coupled to one of the plurality of horizontal local row decoders, at least one but less than all of the plurality of vertical global row decoders being configured to provide a third plurality of predecoded row address signals in response to a third subset of the first bank address, and a corresponding remainder of the vertical global row decoders being configured to provide a fourth plurality of predecoded row address signals in response to a third subset of the second bank address.

A semiconductor memory comprising:

• a plurality of memory arrays each having a plurality of memory cells arranged along rows and columns;
• reconfigurable address decode circuitry coupled to access memory cells in the plurality of memory arrays in response to row and column addresses, wherein each of a plurality of metal mask options configures the reconfigurable address decode circuitry to obtain a different partitioning of the plurality of memory arrays into first and second memory banks such that for each of the plurality of metal masks the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays, the reconfigurable address decode circuitry comprising:
• an array select predecoder configured to select a first memory array in the first memory bank in response to a first subset of a first bank address, and a second memory array in the second memory bank in response to a first subset of a second bank address;
• a first horizontal global row decoder configured to provide a first plurality of predecoded row address signals in response to a second subset of the first bank address;
• a second horizontal global row decoder configured to provide a second plurality of predecoded row address signals in response to a second subset of the second bank address;
• a plurality of horizontal local row decoders each coupled to one of the plurality of memory arrays;
• a plurality of vertical global row decoders each coupled to one of the plurality of horizontal local row decoders, at least one but less than all of the plurality of vertical global row decoders being configured to provide a third plurality of predecoded row address signals in response to a third subset of the first bank address, and a corresponding remainder of the vertical global row decoders being configured to provide a fourth plurality of predecoded row address signals in response to a third subset of the second bank address;
• and
• a plurality of vertical local row decoders each coupled to one of the plurality of horizontal local row decoders, at least one but less than all of the plurality of vertical local row decoders being configured to provide a fifth plurality of predecoded row address signals in response to a fourth subset of the first bank address, and a corresponding remainder of the vertical local row decoders being configured to provide a sixth plurality of predecoded row address signals in response to a fourth subset of the second bank address
• the horizontal local row decoder coupled to the selected first memory array selects a row in the selected first memory array in response to a unique combination of the first, third, and fifth plurality of predecoded decoded row address signals, and
• the horizontal local row decoder coupled to the selected second memory array selects a row in the selected second memory array in response to a unique combination of the second, fourth, and sixth plurality of predecoded row address signals.