Semiconductor memory device having easily redesigned memory capacity
AssigneeRenesas Technology Corp.
InventorNaoya Watanabe
Life of this patent
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Abstract
Sub-blocks SBA0–SBA3, SBB0–SBB3, SBC0–SBC3, SBD0–SBD3 respectively form four groups. In each group, a refresh end signal REF_END is successively transferred to the next sub-block. Therefore, when a refresh counter of the number of bits corresponding to the number of word lines present in a sub-block is provided in a central control circuit, a memory capacity can easily be redesigned by changing the number of sub-blocks and changing a group configuration of sub-blocks. As a result, there can be provided a memory core for embedded memory in which a memory capacity can easily be changed and a refresh control-related circuitry can easily be changed.
Claims7
A semiconductor memory device comprising a plurality of memory banks each having rows that can be activated independently of another memory bank, wherein
- a first memory bank of said plurality of memory banks includes first to N-th sub-memory blocks, where N is a natural number greater than two,
- an M-th sub-memory block, where M is a natural number equal to or greater than two and equal to or smaller than N−1, of said first to N-th sub-memory blocks includes
- a first memory cell array including a plurality of memory cells arranged in rows and columns and
- a first local control circuit, in a refresh mode, starting an operation of successively selecting rows of said first memory cell array in response to a first refresh end signal received from an (M−1)th sub-memory block and instructing a refresh start to an (M+1)th sub-memory block when said operation of successively selecting rows ends, and
- said first memory bank further includes a plurality of sense amplifier bands each shared by adjacent two of said first to N-th sub-memory blocks.
A semiconductor memory device comprising a first memory block, wherein
- said first memory block includes a plurality of sub-memory blocks being refreshed in a circulating manner in a refresh mode,
- each of said plurality of sub-memory blocks includes
- a memory cell array including a plurality of memory cells arranged in rows and columns and
- a local control circuit performing an operation of successively selecting rows of said memory cell array in response to an end of a refresh operation in a sub-memory block at a previous stage which precedes by one in refresh-circulating order of said plurality of sub-memory blocks, and
- a refresh cycle period in each of said plurality of memory blocks is determined depending on a number of said sub-memory blocks included in said first memory block.
Dependencies are inferred from the claim text.