Sense amplifying magnetic tunnel device
AssigneeHewlett-Packard Development Company, L.P.
InventorsFredrick A. Perner, Manish Sharma
Life of this patent
Estimating the term…
Abstract
A sense amplifying magnetic tunnel (SAMT) device is disclosed. In a particular embodiment, a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel is provided. In addition, a spin valve memory (SVM) cell is provided electrically coupled to the gate electrode. The electrical coupling between the SVM cell and the gate electrode serves to provide a control potential to the gate. In addition, the coupling provides a gain to a current passed through the SAMT device.
Claims34
A sense amplifying magnetic tunnel (SAMT) device comprising:
- a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode, and a tunneling gate oxide proximate to the channel;
- and
- a spin valve memory (SVM) cell electrically coupled to the gate electrode.
A sense amplifying magnetic tunnel (SAMT) device comprising:
- a cross-point array of adjustable resistor devices, each resistor device paired with and electrically coupled to an isolator device, the electrical coupling serving to provide a gain to a current passed through the paired adjustable resistor and isolator;
- wherein each of the isolator devices is a field effect transistor (FET), the FET having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel, the adjustable resistor devices being spin valve memory (SVM) cells, each SVM cell electrically coupled to the gate electrode.
A sense amplifying magnetic tunnel (SAMT) device comprising:
- at least one field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel;
- and
- at least one spin valve memory (SVM) cell electrically coupled to the gate electrode of an FET, the SVM cell having:
- a first ferromagnetic layer;
- an intermediate layer in contact with the first layer;
- a second ferromagnetic layer in contact with the intermediate layer opposite from the first ferromagnetic layer.
A computer system comprising:
- a main board;
- at least one central processing unit (CPU) coupled to the main board;
- and
- at least one memory store joined to the CPU by the main board, the memory store including;
- a plurality of parallel electrically conductive rows;
- and
- a plurality of parallel electrically conductive columns crossing the conductive rows, each thereby forming plurality of intersections;
- a plurality of sense amplifying magnetic tunnel (SAMT) devices in electrical contact with and located at an intersection between a conductive row and a conductive column, each SAMT device including:
- a field effect transistor (FET) having a drain, a source, a channel therebetween, a gate electrode and a tunneling gate oxide proximate to the channel;
- and
- a spin valve memory (SVM) cell electrically coupled to the gate electrode of the FET, the SVM cell having:
- a first ferromagnetic layer;
- an intermediate junction layer in contact with the first layer;
- a second ferromagnetic layer in contact with the intermediate layer opposite from the first ferromagnetic layer.
Dependencies are inferred from the claim text.