Semiconductor memory having a first and second sense amplifier for sensing a memory cell voltage during a normal mode and a refresh mode
AssigneeInfineon Technologies AG
InventorJean-Marc Dortu
Life of this patent
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Abstract
Semiconductor memory apparatus and methods of operating the same are provided. The apparatus has at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode and at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode. The apparatus is designed such that either the first or the second sense amplifier can be placed in electrical contact with the memory cell and the capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.
Claims20
A semiconductor memory apparatus, comprising:
- a matrix of memory cells which can be addressed via word lines and bit lines;
- at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode;
- and
- at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode;
- wherein, either the first or the second sense amplifier can be placed in electrical contact with the memory cell, and the capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.
A method for operating a semiconductor memory apparatus, comprising:
- amplifying a voltage level which has been read from a memory cell in the semiconductor memory apparatus using a first sense amplifier when the semiconductor memory apparatus is in an active operating mode;
- and
- amplifying a voltage level which has been read from the memory cell using a second sense amplifier when the semiconductor memory apparatus is in a refresh operating mode;
- wherein a capacitance of the second sense amplifier is lower than the capacitance of the first sense amplifier.
A semiconductor memory apparatus, comprising:
- a plurality of memory cells addressable via word lines and bit lines;
- at least one first sense amplifier for amplifying a voltage level which has been read from a memory cell when the semiconductor memory apparatus is in an active operating mode;
- at least one second sense amplifier for amplifying a voltage level which has been read from the memory cell when the semiconductor memory apparatus is in a refresh operating mode, the second sense amplifier having lower associated capacitance than the first sense amplifier;
- and
- switching circuitry to place either the first or second sense amplifier in electrical contact with the memory cell, depending on whether the device is in the active operating mode or the refresh operating mode.
Dependencies are inferred from the claim text.