US 7,009,900 B2Granted

Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell

AssigneeInfineon Technologies AG

InventorsMatthias Goldbach, Bernhard Sell

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Abstract

A circuit arrangement includes a bit line (10), a reference bit line (12), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor (20, 22) and a p-channel field-effect transistor (30, 32), and also, at the respective source terminals, two voltage sources (40, 42), of which the voltage source (40) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source (42) linked to the p-channel field-effect transistors (30, 32) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell (4) on the bit line (10) if the threshold voltages (UTH1, UTH2) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell (4).

Claims18

Dependent claims

A circuit for reading out, evaluating and rewriting a charge state to a memory cell, the circuit comprising:

a bit line;
a memory cell coupled to the bit line;
a reference bit line;
a reference memory cell for providing a comparison potential, the reference memory cell being coupled to the reference bit line;
a first n-channel field-effect transistor that includes a gate terminal coupled to the bit line and a drain terminal coupled to the reference bit line;
a second n-channel field-effect transistor that includes a gate terminal coupled to the reference bit line and a drain terminal coupled to the bit line;
a first p-channel field-effect transistor that includes a gate coupled to the bit line and a drain terminal coupled to the reference bit line;
a second p-channel field-effect transistor that includes a gate terminal coupled to the reference bit line and a drain terminal coupled to the bit line;
a first voltage source coupled to a source terminal of the first n-channel field effect transistor and to a source terminal of the second n-channel field-effect transistor, the first voltage source for driving a voltage potential from an upper through to a lower limit;
and
a second voltage source coupled to a source terminal of the first p-channel field effect transistor and to a source terminal of the second p-channel field-effect transistor, the second voltage source for driving a voltage potential from the lower through to the upper limit;
wherein the first and second n-channel field-effect transistors have a first threshold voltage and the first and second p-channel field-effect transistors have a second threshold voltage and wherein the magnitudes of the threshold voltages of the first and second n-channel and the first and second p-channel field-effect transistors are in each case greater than half the potential difference between the upper and lower limits of the voltage potential.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/944,536Filed 17 Sep 2004 · continuation
Priority: DE 102 11 93218 Mar 2002
Published: US 2005/0099879 A112 May 2005
Granted: 7 Mar 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 7/062
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of non-latching type, e.g. comparators,…
G11C 7/065
Sense amplifiers; Associated circuits , e.g. timing or triggering circuits: differential amplifiers of latching type
G11C 11/4091
Read-write [R-W] circuits: sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or…
G11C 29/12
Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing: built-in arrangements for testing, e.g.…