Bit line precharge signal generator for memory device
AssigneeHynix Semiconductor Inc.
InventorChang Hyuk Lee
Life of this patent
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Abstract
Disclosed is a bit line precharge signal generator for a memory device, which reduces a resistance component of a signal line by shortening the length of a signal line transferring bit line signals, and reduces an RC time delay. Control signal generator generates a first control signal. A plurality of bit line precharge signal drivers are controlled by first control signal from control signal generator. Each of the bit line precharge signal drivers applies a second signal to the bit line sense amplifier array which is adjacent to bit line precharge signal driver. By using bit line precharge signal generator, a necessary operation is performed within a short time, and unneccessary signal lines are reduced. As a result, a total layout area is reduced.
Claims7
A bit line precharge signal generator for a memory device, the memory device having a plurality of bit line sense amplifier arrays, the bit line precharge signal generator comprising:
- a control signal generator for generating a first control signal;
- and
- a plurality of bit line precharge signal drivers being controlled by the first control signal from the control signal generator,
- wherein each of the bit line precharge signal drivers applies a second signal to the bit line sense amplifier array which is adjacent to the bit line precharge signal driver, and
- wherein the plurality of bit line precharge signal drivers are arranged alternately with respect to the plurality of bit line sense amplifier arrays.
A bit line precharge signal generator for a memory device having a bit line sense amplifier array comprising:
- a control signal generator for generating a bit line precharge enable signal;
- a first precharge driver for generating a first precharge signal to precharge the bit line sense amplifier array in response to the bit line precharge enable signal;
- and
- a second precharge driver for generating a second precharge signal to precharge the bit line sense amplifier array in response to the bit line precharge enable signal;
- wherein the first precharge driver and the second precharge driver are located adjacently to both sides of the bit line sense amplifier array.
Dependencies are inferred from the claim text.