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US 7,009,894 B2Granted
Dynamically activated memory controller data termination
AssigneeIntel Corporation
InventorsAnoop Mukker, Zohar Bogin, Dave Freker, Navneet Dour
Life of this patent
Estimating the term…
Abstract
A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memory, deactivating the termination loads. The method also involves, for a second read of information from the memory, activating the termination loads.
Claims39
A method, comprising:
- by a memory controller:
- for a first read of information from a memory, activating termination loads on said memory controller's side of a data bus between said memory controller and said memory, said activating being a consequence of a first signal's indication of a first clock cycle of a plurality of consecutive clock cycles, a memory read phase being performed by said memory controller over said plurality of clock cycles, said first read of information occurring within said plurality of clock cycles;
- for a write of information into said memory, deactivating said termination loads;
- and,
- for a second read of information from said memory, activating said termination loads.
2 more elements
An apparatus, comprising:
- a memory controller comprising a data bus's termination loads, said data bus to couple to a memory, said termination loads coupled to an output of memory controller logic circuitry, said memory controller logic circuitry to drive said output to place said termination loads in an activated state during a memory read phase and to place said termination loads in a deactivated state during a memory write phase, said memory controller logic circuitry comprising a latch, said latch to latch a first value, said first value to place said termination loads in said activated state, said latch to also provide a second value, said second value to place said termination loads in said deactivated state.
A method, comprising:
- by a computing system:
- for a first read of information from a DDR memory, activating termination loads on said memory controller's side of a data bus between said memory controller and said DDR memory, said activating being a consequence of a first signal's indication of a first clock cycle of a Plurality of consecutive clock cycles, a DDR memory read phase being performed by said memory controller over said plurality of clock cycles, said first read of information occurring within said Plurality of clock cycles;
- for a write of information into said DDR memory, deactivating said termination loads;
- and,
- for a second read of information from said DDR memory, activating said termination loads.
2 more elements
An apparatus, comprising:
- a computing system comprising:
- a memory controller comprising a data bus's termination loads, said data bus coupled to a DDR memory, said termination loads coupled to an output of memory controller logic circuitry, said memory controller logic circuitry to drive said output to place said termination loads in an activated state during a read phase of said DDR memory and to place said termination loads in a deactivated state during a write phase of said DDR memory, said memory controller logic circuitry comprising a latch, said latch to latch a first value, said first value to place said termination loads in said activated state, said latch to also provide a second value, said second value to place said termination loads in said deactivated state.
A machine readable medium having stored thereon a description of a design for a memory controller, the memory controller comprising:
- a data bus's termination loads, said data bus to couple to a memory, said termination loads coupled to an output of memory controller logic circuitry, said memory controller logic circuitry to drive said output to place said termination loads in an activated state during a memory read phase and to place said termination loads in a deactivated state during a memory write phase, said memory controller logic circuitry comprising a latch, said latch to latch a first value, said first value to place said termination loads in said activated state, said latch to also provide a second value, said second value to place said termination loads in said deactivated state.
Dependencies are inferred from the claim text.