Back to results
US 7,009,893 B2Granted
Range selectable address decoder and frame memory device for processing graphic data at high speed using the same
AssigneeNexuschips Co., Ltd.
InventorsHan Jun Choi, Duck Myung Lee, Hag Keun Kim
Life of this patent
Estimating the term…
Abstract
A frame memory device capable of processing graphic data at high speed so as to reduce a burden to be imposed on a processor in a portable terminal of a limited size is disclosed. The frame memory device includes a number of memory cells aligned in a matrix form, and range selectable row/column address decoders capable of designating row/column addresses of a desired range by two addresses, to thereby select a number of memory cells of a desired range all at a time and write data in the selected memory cells.
Claims18
A frame memory device comprising:
- a number of memory cells aligned in a matrix form;
- a range selectable column address decoder for receiving first and second column addresses and generating at least one successive column address selection signal in order to designate at least one successive column address range with respect to the number of memory cells;
- and
- a range selectable row address decoder for receiving first and second row addresses and generating at least one successive row address selection signal in order to designate at least one successive row address range with respect to the number of memory cells,
- wherein a graphic data write operation is accomplished all at a time with respect to the number of memory cells selected by the at least one successive column address selection signal and the at least one successive row address selection signal.
2 more elements
A frame memory device comprising:
- a number of memory cells aligned in a matrix form;
- a range selectable column address decoder for receiving high and low column addresses and generating at least one column address selection signal in order to designate at least one column address range with respect to the number of memory cells;
- and
- a general purpose row address decoder for receiving high and low row addresses and generating two row address selection signals in order to designate two row addresses with respect to the number of memory cells,
- wherein memory cells located from a low column address to a high column address designated by the range selectable column address decoder, are designated on two row lines designated by the general purpose row address decoder according to the input of the high and low row addresses, to thereby write graphic data of two parallel lines that are parallel with the X-axis.
2 more elements
A frame memory device comprising:
- a number of memory cells aligned in a matrix form;
- a range selectable row address decoder for receiving high and low row addresses and generating at least one row address selection signal in order to designate at least one row address range with respect to the number of memory cells;
- and
- a general purpose column address decoder for receiving high and low column addresses and generating two column address selection signals in order to designate two column addresses with respect to the number of memory cells,
- wherein memory cells located from a low row address to a high row address which are designated by the range selectable address decoder, are designated on two column lines designated by the general purpose column address decoder according to the input of the high and low row addresses, to thereby write graphic data of two parallel lines that are parallel with the Y-axis.
2 more elements
A frame memory device comprising:
- a number of memory cells aligned in a matrix form;
- a first general purpose decoder for receiving high and low column addresses and generating two column address selection signals to designate two column addresses with respect to the number of memory cells;
- and
- a second general purpose decoder for receiving high and low row addresses and generating two row address selection signals to designate two row addresses with respect to the number of memory cells,
- wherein graphic data is written by a single write operation all at a time, in four memory cells of a point where two row lines designated by the second general purpose address decoder according to the input of the high and low row addresses and two column lines designated by the first general purpose address decoder according to the input of the high and low column addresses cross-sect each other.
2 more elements
An 8-to-256 range selectable decoder for selecting a successive range value between a high address and a low address when 8-bit high and low addresses are applied thereto, the 8-to-256 range selectable decoder comprises:
- an exclusive OR gate which judges whether or not values of four upper bits in the two high and low address inputs equal one other, and selects only one group if the values of four upper bits equal one another, but selects two or more groups if the values of four upper bits do not equal one another, to thereby generate an output selection signal with respect to a multiplexer;
- a group selection circuit having a first 4-to-16 range selectable address decoder for selecting a range between four upper bits of the two high and low addresses, and generating a low enable signal, a middle enable signal, and a high enable signal which select a low group, a middle group and a high group, respectively, if four upper bits of the two high and low address inputs do not equal one another;
- a second 4-to-16 range selectable decoder for selecting a range value between “1111” and four lower bits of a low address input value in order to select a low address range among 16 addresses in the low group selected by the four lower bits of the low address input;
- a third 4-to-16 range selectable decoder for selecting a range value between “0000” and four lower bits of a high address input value in order to select a high address range among 16 addresses in the high group selected by the four lower bits of the high address input;
- a first multiplexer for selectively outputting any one input among the four lower bits of the low address input and the “0000” to the input terminal of the third 4-to-16 range selectable decoder, according to an output of the group selection circuit;
- a second multiplexer group having 16 multiplexers, in which “0” is input to one input terminal of each multiplexer and a low enable signal is input to the other terminal thereof, and the output of the group selection circuit is input as an output selection signal;
- a third multiplexer group having 16 multiplexers, in which “0” is input to one input terminal of each multiplexer and a middle enable signal is input to the other terminal thereof, and the output of the group selection circuit is input as an output selection signal;
- a fourth multiplexer group having 16 multiplexers, in which the output of the first 4-to-16 range selectable decoder is input to one input terminal of each multiplexer and a high enable signal is input to the other terminal thereof, and the output of the group selection circuit is input as an output selection signal;
- a first AND gate group having 16 AND gates in which the output of the second 4-to-16 range selectable decoder is connected to one terminal of each AND gate and each output of the 16 multiplexers in the second multiplexer group is connected to the other input terminal thereof;
- a second AND gate group having 16 AND gates in which 16′hffff is applied to one terminal of each AND gate and each output of the 16 multiplexers in the third multiplexer group is connected to the other input terminal thereof, in order to output “1” to all outputs of the 16 AND gates, so that all addresses between the selected low and high addresses are selected;
- a third AND gate group having 16 AND gates in which the output of the third 4-to-16 range selectable decoder is connected to one terminal of each AND gate and each output of the 16 multiplexers in the fourth multiplexer group is connected to the other input terminal thereof;
- and
- an OR gate for logically summing the outputs of the first through third gate groups.
10 more elements
Dependencies are inferred from the claim text.