Low voltage, island-layer-based nonvolatile semiconductor storage device with floating biased memory cell channel

A method for driving a nonvolatile memory device comprising a semiconductor substrate, at least one island semiconductor layer provided on the semiconductor substrate, at least one memory cell having a control gate and a charge storage layer partly or entirely surrounding a peripheral surface of the island semiconductor layer, a selection transistor provided between the memory cell and the semiconductor substrate and having an insulation layer and a selection gate, a source diffusion layer provided as a source between the semiconductor substrate and the island semiconductor layer provided with the memory cell and the selection transistor for electrically isolating the island semiconductor layer from the semiconductor substrate, and a drain diffusion layer provided as a drain in an end surface of the island semiconductor layer opposite from the source diffusion layer with respect to the memory cell, the method comprising the steps of:

• applying a negative first voltage to the drain and the selection gate, and applying 0V or a positive second voltage to the source;
• and
• applying a positive third voltage to the control gate of the memory cell,
• whereby electric charges are injected into the charge storage layer.

A semiconductor storage device comprising:

• a nonvolatile memory device comprising a semiconductor substrate, at least one island semiconductor layer provided on the semiconductor substrate, at least one memory cell having a control gate and a charge storage layer partly or entirely surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the semiconductor substrate and having a first insulation layer and a first selection gate, a source diffusion layer provided as a source between the semiconductor substrate and the island semiconductor layer provided with the memory cell and the first selection transistor for electrically isolating the island semiconductor layer from the semiconductor substrate, a drain diffusion layer provided as a drain in an end surface of the island semiconductor layer opposite from the source diffusion layer with respect to the memory cell, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second insulation layer and a second selection gate;
• a first voltage generating section which generates a voltage to be applied to the control gate;
• a second voltage generating section which generates a voltage to be applied to the first selection gate;
• a third voltage generating section which generates a voltage to be applied to the drain;
• a fourth voltage generating section which generates a voltage to be applied to the source;
• a fifth voltage generating section which generates a voltage to be applied to the second selection gate;
• and
• a state controlling section which controls the voltages generated by the first to fifth voltage generating sections and timing for the application of the voltages;
• wherein the state controlling section controls the first to fifth voltage generating sections to cause the second voltage generating section and the third voltage generating section to generate a negative first voltage to apply the first voltage to the first selection gate and the drain, to cause the fifth voltage generating section to generate a positive second voltage to apply the second voltage to the second selection gate, to cause the fourth voltage generating section to generate 0V or a positive third voltage to apply 0V or the third voltage to the source, and to cause the first voltage generating section to generate a positive fourth voltage higher than the second voltage to apply the fourth voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.