MRAM and data writing method therefor
AssigneeNEC Electronics Corporation
InventorTakeshi Okazawa
Life of this patent
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Abstract
In an MRAM having main and sub-structures, selecting transistors are arranged so as to meet the arrangement order of main word lines, sub-word lines and the selecting transistors. The selecting transistor is driven to cause a snap back phenomenon to occur. As a result, data can be written to a memory cell using a substrate current, not a channel current. Moreover, a data may be written into a selected memory cell by discharge the charge which is charged in the main and sub word lines corresponding to the memory cell.
Claims10
A Magnetic random access memory (MRAM), comprising:
- a first wiring through which a write current is caused to flow in one direction;
- a selecting transistor having a first electrode connected to the first wiring and a second electrode connected to a power voltage potential supply node for controlling the write current;
- and
- a plurality of magnetic memory cells each arranged on the first wiring, one end of the plurality of magnetic memory cells being connected to the first wiring.
The memory as claimed in 1, wherein the other end of the plurality of MRAM cells are connected to a second wiring through which a current is caused to flow in both directions.
A MRAM, comprising:
- a main bit line;
- a sub-bit line having one end connected to said main bit line;
- a main word line;
- a sub-word line having one end connected to said main word line;
- a MRAM cell provided between said sub-word line and said sub-bit line;
- and
- a select transistor coupled to the other end of one of said sub-word and said sub-bit lines.
A MRAM, comprising:
- a plurality of first sub-row lines extending in a first direction;
- a plurality of first sub-column lines extending in a second direction different from the first direction;
- a first memory cell array including a plurality of first magnetic memory cells each arranged at crossing points between a corresponding one of said first sub-row lines and a corresponding one of said first sub-column lines;
- a plurality of second sub-row lines extending in the first direction;
- a plurality of second sub-column lines extending in the second direction;
- a second memory cell array including a plurality of second magnetic memory cells each arranged at crossing points between a corresponding one of said second sub-row lines and a corresponding one of said second sub-column lines;
- a plurality of third sub-row lines extending in the first direction;
- a plurality of third sub-column lines extending in the second direction;
- a third memory cell array including a plurality of third magnetic memory cells each arranged at crossing points between a corresponding one of said third sub-row lines and a corresponding one of said third sub-column lines;
- a plurality of main row lines provided in common to said first and second memory cell arrays;
- and
- a plurality of main column lines provided in common to said first and third memory cell arrays,
- wherein each of the plurality of first sub-row lines of the first memory cell array has two end portions, and one of the two end portions is connected to one of the main row lines, and the other end portion of the two end portions is connected to a first row selecting transistor, and
- each of the plurality of sub-column lines of the first memory cell array has two end portions, and one of the two end portions is connected to one of the main column lines through a column selecting transistor, and the other end portion of the two end portions is connected to a write circuit.
Dependencies are inferred from the claim text.