Stable memory cell

A memory cell comprising:

• a first data node switchably coupled to a first bit line, and a second data node switchably coupled to a second bit line, wherein the memory cell is configured to be read by coupling the first data node to the first bit line and coupling the second data node to the second bit line to enable a low voltage at one of the data nodes to pull down the corresponding bit line, wherein the first bit line is switchably coupled to a first low voltage, and wherein when the memory cell is read, the first bit line is coupled to the first low voltage when a voltage at the second data node is high and decoupled from the first low voltage when the voltage at the second data node is low;
• first and second transistors serially coupled between the first bit line and the first low voltage, wherein the first transistor is switched on when the voltage at the second data node is high and switched off when the voltage at the second data node is low, and wherein the second transistor is switched on when the voltage on a word line is high and switched off when the voltage on the word line is low;
• and
• a first delay element coupled between the second transistor and the word line to cause the second transistor to be switched on at a first delay after the voltage on the word line goes high and switched off at a first delay after the voltage on the word line goes low.

A memory cell comprising;

• a first data node switchably coupled to a first bit line, and a second data node switchably coupled to a second bit line, wherein the memory cell is configured to be read by coupling the first data node to the first bit line and coupling the second data node to the second bit line to enable a low voltage at one of the data nodes to pull down the corresponding bit line, wherein the first bit line is switchably coupled to a first low voltage, and wherein when the memory cell is read, the first bit line is coupled to the first low voltage when a voltage at the second data node is high and decoupled from the first low voltage when the voltage at the second data node is low, wherein the second bit line is switchably coupled to a second low voltage and wherein when the memory cell is read, the second bit line is coupled to the second low voltage when a voltage at the first data node is high and decoupled from the second low voltage when the voltage at the first data node is low;
• third and fourth transistors serially coupled between the second bit line and the second low voltage, wherein the third transistor is switched on when the voltage at the second data node is high and switched off when the voltage at the second data node is low, and wherein the fourth transistor is switched on when the voltage on a word line is high and switched off when the voltage on the word line is low, and
• a second delay element coupled between the fourth transistor and the word line to cause the fourth transistor to be switched on at a second delay after the voltage on the word line goes high and switched off at a second delay after the voltage on the word line goes low.

A method implemented in a memory cell comprising:

• providing a memory cell having a first data node switchably coupled to a first bit line and a second data node switchably coupled to a second bit line, wherein the memory cell is configured to be read by enabling a low voltage at one of the data nodes to pull down the corresponding bit line and wherein a plurality of transistors that form the memory cell have nominally the same threshold voltage but have high threshold voltage variations;
• switchably coupling the first bit line to a first low voltage;
• and
• when the memory cell is read,
• coupling the first bit line to the first low voltage when the second data node is high and
• decoupling the first bit line from the first low voltage when the second data node is low.

A method implemented in a memory cell comprising;

• providing a memory cell having a first data node switchably coupled to a first bit line and a second data node switchably coupled to a second bit line, wherein the memory cell is configured to be read by enabling a low voltage at one of the data nodes to pull down the corresponding bit line;
• switchably coupling the first bit line to a first low voltage;
• and
• when the memory cell is read,
• coupling the first bit line to the first low voltage with a first delay after the second data node goes high and decoupling the first bit line from the first low voltage with the first delay after the second data node goes low.

A memory cell comprising:

• first and second inverters, wherein the input of the first inverter and the output of the second inverter are coupled to a first data node and wherein the output of the first inverter and the input of the second inverter are coupled to a second data node;
• first and second bit lines;
• first and second transfer transistors, wherein the first transfer transistor is coupled between the first data node and the first bit line, wherein the second data transfer transistor is coupled between the second data node and the second bit line, and wherein the first and second transfer transistors are coupled to a word line and configured to be switched on and off by a signal on the word line;
• and
• a first pair of additional transistors, wherein the first pair of additional transistors is serially coupled between the second bit line and a predetermined voltage, wherein a first of one of the first pair of additional transistors is coupled to the word line and configured to be switched on and off by the signal on the word line, and wherein a second one of the first pair of additional transistors is coupled to the first data node and configured to be switched on and off by a voltage at the first data node;
• wherein the plurality of transistors that form the memory cell have nominally the same threshold voltage but have high threshold voltage variations.