Dynamic memory cell

#This application claims foreign priority benefits under 35 U.S.C. §119 to co-pending German patent application 102 55 203.7-53, filed Nov. 27, 2002. This related patent application is herein incorporated by reference.

#1. Field of the Invention

#The invention relates to a dynamic memory cell for use in a DRAM memory.

#Preferred embodiments of the invention are explained in more detail below with reference to the accompanying drawings, in which:

#FIG. 1 shows an electrical diagram with components of a dynamic memory cell in accordance with a preferred embodiment of the invention;

#FIG. 2 shows a detail from a DRAM memory with memory cells in accordance with an embodiment of the invention with twisted bit lines;

#FIG. 1 illustrates a dynamic memory cell according to the invention. The memory cell has a storage capacitor C, the first terminal of which is connected to a first bit line BL1 of a bit line BLP via a first selection transistor T1. A second terminal of the storage capacitor C is connected to a second bit line BL2 of the bit line pair BLP via a second selection transistor T2. Control terminals of the first selection transistor T1 and of the second selection transistor T2 can be driven via a word line WL. The selection transistors T1, T2 are preferably designed as n-channel field-effect transistors, so that the selection transistors T1, T2 are turned on in the event of a HIGH potential on the word line WL.

#If the selection transistors are in the on state, then the charge stored in the storage capacitor C flows equally onto the first bit line BL1 and the second bit line BL2. The two bit lines BL1, BL2 of the bit line pair BLP have previously been equalized to a center potential by means of a charge equalizing device (not shown).

#The first bit line BL1 and the second bit line BL2 of the bit line pair BLP are connected to a sense amplifier 1 at one end. The sense amplifier is configured in such a way that it detects a charge difference between the two bit lines BL1, BL2 of the bit line pair BLP and increases the potential of the bit line with the higher charge and decreases the potential of the bit line with the lower charge. By virtue of the fact that the charge stored in the storage capacitor is applied to both bit lines equally and simultaneously, the result is a symmetrical opposite signal profile around the center potential on the two bit lines.