Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
AssigneeTexas Instruments Incorporated
InventorSudhir Kumar Madan
Life of this patent
Estimating the term…
Abstract
Ferroelectric memory devices and methods are provided, wherein a cell plateline signal is applied to a ferroelectric target cell capacitor and a zero cancellation capacitor is coupled with a bitline during a memory read operation. A negative pulse is applied to the zero cancellation capacitor during the cell plateline pulse to reduce the voltage on the bitline, thereby facilitating reduced cell plateline voltage levels while still allowing a high percentage of the ferroelectric saturation voltage to be applied across the ferroelectric cell capacitor.
Claims49
A method of reading data from a ferroelectric memory cell, the method comprising:
- coupling a first ferroelectric cell capacitor terminal to an array bitline;
- activating a cell plateline signal to a second ferroelectric cell capacitor terminal to provide a voltage across the ferroelectric cell capacitor;
- coupling a first zero cancellation capacitor terminal to the array bitline;
- and
- providing a zero cancellation plateline signal to a second zero cancellation capacitor terminal while the cell plateline signal is activated, the zero cancellation plateline signal comprising a first pre-determined voltage level during a first time period and a second pre-determined voltage level during a second time period, wherein the first voltage level is greater than the second voltage level.
A method of reading data from a ferroelectric memory cell, the method comprising:
- coupling a first ferroelectric cell capacitor terminal to an array bitline;
- activating a cell plateline signal to a second ferroelectric cell capacitor terminal to provide a voltage across the ferroelectric cell capacitor;
- coupling a first zero cancellation capacitor terminal to the array bitline;
- and
- providing a zero cancellation plateline signal to a second zero cancellation capacitor terminal while the cell plateline signal is activated, the zero cancellation plateline signal comprising a first voltage level during a first time period, a second voltage level during a second time period, and a third voltage level during a third time period, wherein the first and third voltage levels are greater than the second voltage level.
A system for reading data using reduced plateline voltages in a ferroelectric memory device, the system comprising:
- a zero cancellation capacitor having first and second terminals;
- a zero cancellation switching device coupled with the zero cancellation capacitor, the zero cancellation switching device selectively coupling the first zero cancellation capacitor terminal with an array bitline according to a zero cancellation wordline signal;
- and
- a control system coupled with the zero cancellation capacitor and the zero cancellation switching device, the control system providing the zero cancellation wordline signal to the zero cancellation switching device and providing a negative pulse of a pre-determined magnitude to the second zero cancellation capacitor terminal while a cell plateline signal is activated to create a voltage across a target ferroelectric cell capacitor.
A ferroelectric memory device, comprising:
- an array of ferroelectric memory cells arranged in rows and columns, the cells individually comprising at least one ferroelectric cell capacitor having first and second terminals and at least one cell transistor adapted to selectively couple the first cell capacitor terminal to one of a pair of array bitlines associated with an array column according to an array wordline, wherein rows of the memory cells are coupled with a corresponding wordline;
- a zero cancellation system coupled with the array, the zero cancellation system comprising a plurality of zero cancellation circuits individually coupled with the array bitlines, the zero cancellation circuits individually comprising a zero cancellation capacitor having first and second terminals, and a zero cancellation switching device coupled with the zero cancellation capacitor, the zero cancellation switching device selectively coupling the first zero cancellation capacitor terminal with an array bitline according to a zero cancellation wordline signal;
- and
- a control system coupled with the zero cancellation capacitor and the zero cancellation switching device, the control system providing the zero cancellation wordline signal to the zero cancellation switching device and providing a negative pulse of a pre-determined magnitude to the second zero cancellation capacitor terminal while a cell plateline signal is activated to provide a voltage across a target ferroelectric cell capacitor.
Dependencies are inferred from the claim text.