Video signal detecting circuit for adjusting sync signals with a mean difference of the number of pixels from a standard

A video signal detecting circuit comprising:

• a synchronization detector for detecting a vertical synchronous signal and a horizontal synchronous signal in an input video signal;
• a first counter for starting incrementing in response to the vertical synchronous signal detected while outputting a first signal representative of an incrementing value, and stopping incrementing when the incrementing value reaches a first predetermined value;
• a second counter for starting incrementing in response to the horizontal synchronous signal following the vertical synchronous signal detected, and counting the detected horizontal synchronous signals to output a second signal representative of a count;
• a first comparator for comparing the second signal with the first signal for outputting a third signal representative of a resulting difference between the second and first signals;
• a third counter for start counting pixel clock pulses in response to each of the horizontal synchronous signals detected, and outputting a fourth signal when a count reaches a second predetermined value;
• a second comparator for comparing the horizontal synchronous signal detected with the fourth signal for outputting a fifth signal representative of a resulting difference between the horizontal synchronous signal detected and the fourth signal;
• a mean circuit for averaging the fifth signals over a plurality of lines of the input video signal to produce a mean value resultant from averaging;
• and
• an adjusting circuit for adjusting the detected horizontal synchronous signal with the mean value for outputting a resulting adjusted signal as a horizontal synchronous signal;
• the first predetermined value and the second predetermined value being respectively substantially equal to a standard number of lines included in a single picture and a standard number of pixels included in a single line.